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SPMC75F2413A
16-bit MCU with Two Channels Motor Controller
Feb. 16, 2006 Version 1.1
Sunplus Innovation Technology reserves the right to change this documentation without prior notice. Information provided by Sunplus Innovation Technology is believed to be accurate and reliable. However, Sunplus Innovation Technology makes no warranty for any errors which may appear in this document. In addition, SunplusIT products are Contact Sunplus Innovation Technology to obtain the latest version of device specifications before placing your order. No responsibility is assumed by Sunplus Innovation Technology for any infringement of patent or other rights of third parties which may result from its use. reasonably be expected to result in significant injury to the user, without the express written approval of SunplusIT. not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
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Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 7 2. FEATURES.................................................................................................................................................................................................. 7 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 8 4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 9 4.1. PIN DESCRIPTIONS ................................................................................................................................................................................ 9 4.1.1. 80-Pin QFP/ 64-Pin QFP package signals description ............................................................................................................. 9 4.2. PIN ASSIGNMENT ..................................................................................................................................................................................11 4.2.1. 80-Pin QFP Package ...............................................................................................................................................................11 4.2.2. 64-Pin QFP Package .............................................................................................................................................................. 12 5. FUNCTIONAL DESCRIPTIONS................................................................................................................................................................ 13 5.1. CPU CORE.......................................................................................................................................................................................... 13 5.2. MEMORY ORGANIZATION...................................................................................................................................................................... 13 5.2.1. Memory Map ........................................................................................................................................................................... 13 5.2.2. Flash Organization and Control .............................................................................................................................................. 14 5.2.3. SRAM...................................................................................................................................................................................... 18 5.2.4. Reset and Interrupt Vectors .................................................................................................................................................... 18 5.3. CLOCK GENERATION MODULE (CGM) .................................................................................................................................................. 32 5.3.1. Crystal Oscillator ..................................................................................................................................................................... 32 5.3.2. Phase-lock Loop (PLL) ........................................................................................................................................................... 32 5.3.3. External clock.......................................................................................................................................................................... 32 5.3.4. Clock Monitoring ..................................................................................................................................................................... 32 5.3.5. RC Oscillator........................................................................................................................................................................... 34 5.4. POWER SAVING MODES ....................................................................................................................................................................... 34 5.4.1. Wake-up Sources.................................................................................................................................................................... 35 5.5. INTERRUPT .......................................................................................................................................................................................... 37 5.5.1. Interrupt Source ...................................................................................................................................................................... 37 5.5.2. Interrupt procedure ................................................................................................................................................................. 39 5.6. RESET MANAGEMENT .......................................................................................................................................................................... 42 5.6.1. Power on reset (POR)............................................................................................................................................................. 42 5.6.2. External reset.......................................................................................................................................................................... 42 5.6.3. Low voltage reset (LVR).......................................................................................................................................................... 43 5.6.4. Watchdog timer reset (WDTR)................................................................................................................................................ 43 5.6.5. Illegal address reset (IAR) ...................................................................................................................................................... 43 5.6.6. Illegal instruction reset (IIR) .................................................................................................................................................... 43 5.7. GENERAL PURPOSE I/O PORTS (GPIO)................................................................................................................................................ 46 5.8. TIMER/PWM MODULE (TPM)............................................................................................................................................................... 55 5.9. PDC TIMER 0 AND 1 ......................................................................................................................................................................... 55 5.9.1. Module Introduction ................................................................................................................................................................ 55 5.9.2. PDC Timer Counting Operation .............................................................................................................................................. 57 5.9.3. Phase Counting Mode Operation............................................................................................................................................ 74 5.9.4. Position Detection Change (PDC) Mode Operation................................................................................................................ 77
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5.10. TPM TIMER 2 MODULE .................................................................................................................................................................... 80 5.10.1. Introduction........................................................................................................................................................................... 80 5.10.2. TPM Timer 2 Counting Operation......................................................................................................................................... 81 5.11. MCP TIMER 3 AND 4 MODULE ......................................................................................................................................................... 95 5.11.1.Introduction ............................................................................................................................................................................. 95 5.11.2.MCP Timer 3 and 4 Counting Operation................................................................................................................................. 97 5.12. COMPARE MATCH TIMER .....................................................................................................................................................................119 5.13. TIME BASE MODULE........................................................................................................................................................................... 121 5.14. SERIAL COMMUNICATION INTERFACE .................................................................................................................................................. 122 5.14.1. SPI (Standard Peripheral Interface) ................................................................................................................................... 122 5.14.2. SPI Operation..................................................................................................................................................................... 123 5.14.3. UART (Universal Asynchronous Receiver/Transceiver)..................................................................................................... 127 5.14.4. UART Operation ................................................................................................................................................................. 127 5.15. ANALOG-TO-DIGITAL CONVERTER (ADC)............................................................................................................................................ 132 5.16. WATCHDOG TIMER (WDT) ................................................................................................................................................................. 137 6. ELECTRICAL SPECIFICATIONS ........................................................................................................................................................... 140 6.1. ABSOLUTE MAXIMUM RATINGS ........................................................................................................................................................... 140 6.2. DC CHARACTERISTICS (VDD = 4.5~5.5V, TA = -40~85C) .................................................................................................................. 140 6.3. AC CHARACTERISTICS (VDD = 4.5~5.5V, TA = -40~85C) .................................................................................................................. 140 6.4. ANALOG INTERFACE ELECTRICAL CHARACTERISTICS (VDD = 5.0V, TA = -40C~85C) ......................................................................... 141 7. SPMC75F2413A EVM BOARD V1.1 SCHEMATIC ................................................................................................................................. 142 8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................. 145 8.1. PACKAGE INFORMATION ..................................................................................................................................................................... 145 8.1.1. 80 PIN QFP........................................................................................................................................................................... 145 8.1.2. 64 PIN QFP........................................................................................................................................................................... 146 8.2. ORDERING INFORMATION ................................................................................................................................................................... 146 8.3. STORAGE CONDITION AND PERIOD FOR PACKAGE ............................................................................................................................... 147 8.4. RECOMMENDED SMT TEMPERATURE PROFILE.................................................................................................................................... 147 9. DISCLAIMER........................................................................................................................................................................................... 148 10. REVISION HISTORY ............................................................................................................................................................................... 149
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Figures
PAGE
Figure 3-1 SPMC75F2413A function block diagram .............................................................................................................................. 8 Figure 4-1 SPMC75F2413A QFP80 package .......................................................................................................................................11 Figure 4-2 SPMC75F2413A QFP64 package ...................................................................................................................................... 12 Figure 5-1 Memory allocation ............................................................................................................................................................... 13 Figure 5-2 Structure of Information block ............................................................................................................................................. 14 Figure 5-3 Page0 and frame of flash .................................................................................................................................................... 14 Figure 5-4 Power-up procedure............................................................................................................................................................ 17 Figure 5-5 The crystal circuit connection.............................................................................................................................................. 32 Figure 5-6 PLL and external clock block diagram ................................................................................................................................ 32 Figure 5-7 The external clock from oscillator connection ..................................................................................................................... 32 Figure 5-8 Clock Fail timing.................................................................................................................................................................. 33 Figure 5-9 Wait mode timing ................................................................................................................................................................ 34 Figure 5-10 Standby mode timing......................................................................................................................................................... 35 Figure 5-11 Interrupt procedure timing ................................................................................................................................................. 39 Figure 5-12 Stack memory operation with interrupt procedure............................................................................................................. 40 Figure 5-13 External reset circuit.......................................................................................................................................................... 42 Figure 5-14 Power-on reset, external reset and power-up timer timing ............................................................................................... 43 Figure 5-15 Low voltage reset timing ................................................................................................................................................... 44 Figure 5-16 Watchdog timer reset timing ............................................................................................................................................. 44 Figure 5-17 Illegal address reset timing ............................................................................................................................................... 45 Figure 5-18 Illegal instruction reset timing............................................................................................................................................ 45 Figure 5-19 IO structure diagram ......................................................................................................................................................... 47 Figure 5-20 GPIO input/output timing................................................................................................................................................... 48 Figure 5-21 Keychange timing.............................................................................................................................................................. 48 Figure 5-22 PDC timers block diagram ................................................................................................................................................ 56 Figure 5-23 Continuous up counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b) ....................................................... 58 Figure 5-24 shows the normal continuous up counting mode for edge-aligned PWM generation of timer 0. ...................................... 59 Figure 5-25 Edge-Aligned mode PWM................................................................................................................................................. 60 Figure 5-26 Example programming flowchart of PWM compare match output operation.................................................................... 60 Figure 5-27 TMR0 edge aligned PWM ................................................................................................................................................. 61 Figure 5-28 Timer mode output timing.................................................................................................................................................. 62 Figure 5-29 Continuous up/down counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b).............................................. 63 Figure 5-30 Center-aligned mode PWM............................................................................................................................................... 63 Figure 5-31 TMR0 center aligned PWM ............................................................................................................................................... 64 Figure 5-32 input capture signal connected to TIO0A .......................................................................................................................... 65 Figure 5-33 Example programming flowchart of input capture operation............................................................................................. 66 Figure 5-34 Capture input signal width and cycle................................................................................................................................. 67 Figure 5-35 phase counting mode 1..................................................................................................................................................... 74 Figure 5-36 phase counting mode 2..................................................................................................................................................... 75 Figure 5-37 phase counting mode 3..................................................................................................................................................... 75 Figure 5-38 phase counting mode 4..................................................................................................................................................... 76 Figure 5-39 Example programming flowchart of phase counting operation ......................................................................................... 76 Figure 5-40 Example programming flowchart of PDC operation .......................................................................................................... 77 Figure 5-41 Position detection with noise filter ..................................................................................................................................... 78 Figure 5-42 TPM timer 2 block diagram ............................................................................................................................................... 80 Figure 5-43 Continuous up counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b) ....................................................... 82 (c) Sunplus Innovation Technology Inc. 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Figure 5-44 Edge-Aligned mode PWM................................................................................................................................................. 82 Figure 5-45 Example programming flowchart of PWM compare match output operation.................................................................... 83 Figure 5-46 TMR2 edge aligned PWM ................................................................................................................................................. 84 Figure 5-47 Timer mode output timing.................................................................................................................................................. 85 Figure 5-48 Continuous up/down counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b).............................................. 86 Figure 5-49 Center-Aligned mode PWM .............................................................................................................................................. 86 Figure 5-50 TMR2 center aligned PWM ............................................................................................................................................... 87 Figure 5-51 input capture signal connected to TIO2A .......................................................................................................................... 88 Figure 5-52 Example programming flowchart of input capture operation............................................................................................. 89 Figure 5-53 Capture input signal width and cycle................................................................................................................................. 90 Figure 5-54 MCP timer 3 and 4 block diagram..................................................................................................................................... 95 Figure 5-55 Continuous up counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b) ....................................................... 97 Figure 5-56 Edge-Aligned mode PWM................................................................................................................................................. 98 Figure 5-57 Continuous up/down counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b).............................................. 98 Figure 5-58 Center-Aligned mode PWM .............................................................................................................................................. 99 Figure 5-59 Example programming flowchart of PWM operation....................................................................................................... 106 Figure 5-60 PWM output timing with different duty mode selection ................................................................................................... 107 Figure 5-61 Output polarity timing ...................................................................................................................................................... 108 Figure 5-62 PWM Sync mode ............................................................................................................................................................ 109 Figure 5-63 shows the center-aligned complementary PWM with dead time inserted of timer 3........................................................111 Figure 5-64 Active-low PWM mode of dead-time generation ..............................................................................................................111 Figure 5-65 Fault error timing ..............................................................................................................................................................113 Figure 5-66 Output compare error.......................................................................................................................................................113 Figure 5-67 Oscillator stopped timing..................................................................................................................................................114 Figure 5-68 Stop PWM output only when overload occurs .................................................................................................................116 Figure 5-69 Stop all output when overload occurs ..............................................................................................................................117 Figure 5-70 CMT timing.......................................................................................................................................................................119 Figure 5-71 Timebase and buzzer output timing ................................................................................................................................ 121 Figure 5-72 Function block diagram of SPI interface ......................................................................................................................... 123 Figure 5-73 SPI mode timing, Master Mode....................................................................................................................................... 124 Figure 5-74 SPI mode timing, Slave Mode, SPIPHA = 0.................................................................................................................... 125 Figure 5-75 UART block diagram ....................................................................................................................................................... 128 Figure 5-76 UART Data Format.......................................................................................................................................................... 128 Figure 5-77 Data Transmission Timing............................................................................................................................................... 128 Figure 5-78 Data sampling scheme.................................................................................................................................................... 129 Figure 5-79 RX buffer full ................................................................................................................................................................... 129 Figure 5-80 Overrun error timing ........................................................................................................................................................ 130 Figure 5-81 Parity Error timing ........................................................................................................................................................... 130 Figure 5-82 Frame Error timing .......................................................................................................................................................... 130 Figure 5-83 ADC equivalent circuit for SPMC75F2413A.................................................................................................................... 133 Figure 5-84 ADC timing diagram ........................................................................................................................................................ 133 Figure 5-85 AD conversion timing ...................................................................................................................................................... 135 Figure 5-86 Watchdog Timing Diagram.............................................................................................................................................. 138 Figure 7-1 SPMC75F2413A EVM board circuit part I......................................................................................................................... 142 Figure 7-2 SPMC75F2413A EVM board circuit part II........................................................................................................................ 143 Figure 7-3 SPMC75F2413A EVM board circuit part III....................................................................................................................... 144
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Tables
PAGE
Table 5-1 Detailed Address Mapping.................................................................................................................................................... 13 Table 5-2 Command function and access flow..................................................................................................................................... 14 Table 5-3 Flash/SRAM access table in normal and ICE mode............................................................................................................. 17 Table 5-4 Interrupts vectors list............................................................................................................................................................. 18 Table 5-5 the relationship between mode and operation...................................................................................................................... 34 Table 5-6 Interrupt sources of each IRQ level ...................................................................................................................................... 38 Table 5-7 Reset source and effected modules ..................................................................................................................................... 43 Table 5-8 Open-drain Configuration ..................................................................................................................................................... 46 Table 5-9 I/O Configuration................................................................................................................................................................... 46 Table 5-10 PDC timers specification..................................................................................................................................................... 56 Table 5-11 Input capture configuration settings and results ................................................................................................................. 65 Table 5-12 phase counting mode 1 relationship................................................................................................................................... 74 Table 5-13 phase counting mode 2 relationship................................................................................................................................... 75 Table 5-14 phase counting mode 3 relationship................................................................................................................................... 75 Table 5-15 phase counting mode 4 relationship................................................................................................................................... 76 Table 5-16 TPM Timer 2 Specification .................................................................................................................................................. 80 Table 5-17 input capture configuration settings and results ................................................................................................................. 88 Table 5-18 MCP timer 3 and 4 specification ......................................................................................................................................... 95 Table 5-19 Fault input and PWM output pins combinations ................................................................................................................112 Table 5-20 Overload protection interrupt when POLP = 1...................................................................................................................117 Table 5-21 Overload protection interrupt when POLP = 0...................................................................................................................118 Table 5-22 P_UART_BaudRate setup value at FCK = 24.0 MHz ...................................................................................................... 127 Table 5-23 WDT Time-out selections.................................................................................................................................................. 138
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16-BIT MCU WITH TWO CHANNELS MOTOR CONTROLLER
1. GENERAL DESCRIPTION
The SPMC75F2413A, a 16-bit architecture product, carries the newest 16-bit microprocessor, Twelve 16-bit motor drive PWM outputs (MCP) - 2-channel motor drive PWM outputs (3-phase 6-pin complementary PWM outputs) - Center- or Edge-aligned PWM outputs - PWM overload protection with external OL1/OL2 input pins - Emergency PWM outputs shutdown with external fault protection pins - Programmable dead-time control - PWM service and fault interrupt generation - Capable of driving AC induction and BLDC motors Five 16-bit general-purpose timers (TPM) - Timer 0/1 each supports 3-channel Capture/Compare/PWM function - Timer function - Timer 3/4 supports motor drive PWM function 2 supports 2-channel Capture/Compare/PWM
'nSPTM
(pronounced
as The
micro-n-SP), developed by Sunplus Innovation Technology. complex digital signal processes easily and rapidly. SRAM.
high processing speed assures the 'nSPTM is capable of handling The memory capacity includes 32K-word flash memory plus a 2K-word working Also, a 2-channel motor driver is incorporated which can Other features include PLL, 64 programmable drive two BLDC (Brushless DC) or AC induction motors simultaneously. multi-functional I/Os, UART, SPI, five 16-bit general-purpose timers, two compare match timers, low voltage reset, 8-ch 10-bit ADC input and many others. machines, or refrigerators. The device is suitable for home appliances with motors, such as air conditioners, washing
2. FEATURES
SunplusIT 16-bit 'nSP processor (ISA 1.2) Operating voltage: - 4.5V ~ 5.5V Operating speed: 12~24MHz Operating temperature: -40~85 On-chip Memory - 32KW (32K*16) Flash - 2KW (2K*16) SRAM Clock for system operation - Crystal oscillator, On-chip PLL and external clock for clock generation - Monitoring for clock failed Power management - 2 power-down modes: Wait/Standby - Each peripheral can be powered down independently Up to 38 interrupt sources Up to 6 reset status flag Up to 64 GPIO pins
Two Compare Match Timers One Timebase timer 10-bit analog-to-digital converter - 8 multiplexed input channels - 10s (100kHz) conversion time - Support top reference voltage input Serial communication interface - UART - SPI Watchdog timer Embedded In-Circuit-Emulation Circuit
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3. BLOCK DIAGRAM
3~6MHz Crystal XTAL2 XTAL1 IOA15/ VEXTREF ADCTRG
Clock Generation Module
PLL Clock Monitor
8-ch 10-bit ADC LVR Serial Interface SPI/UART Interrupt Control Module GPIO PortC PortA
RESETB ICEN ICECLK ICESDA
Reset Management
PortB
unSP 16-bit CPU+ICE
Watchdog TPM Module Compare Match Timer
Information Block 64x16 Embedded Flash
PortD
Main Block 32Kx16 Embedded Flash
2Kx16 SRAM
FLASH control
CLK200K
ROS C
Figure 3-1 SPMC75F2413A function block diagram
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4. SIGNAL DESCRIPTIONS
4.1. Pin Descriptions 4.1.1. 80-Pin QFP/ 64-Pin QFP package signals description
PIN No Mnemonic QFP80 QFP64 ICEN ICECLK ICESDA IOD0/ICECLK IOD1/ICESDA IOD2 RESETB IOD3 NC NC IOB0/TIO3F/W1N IOB1/TIO3E/V1N IOB2/TIO3D/U1N IOB3/TIO3C/W1 IOB4/TIO3B/V1 IOB5/TIO3A/U1 IOB6/FTIN1 IOB7/OL1 IOB8/TIO0C IOB9/TIO0B IOB10/TIO0A IOB11/SCK IOB12/SDI/RXD1 IOB13/SDO/TXD1 IOB14 IOB15 IOD12 IOD13 IOD14 IOD15 IOA8 IOA9/TIO2A IOA10/TIO2B IOA11/TCLKA IOA12/TCLKB IOA13/TCLKC IOA14/TCLKD IOA15/ADCTRG VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I (PL) I/O I/O I/O I/O I/O I (PH) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P P ICE/Program or Normal mode control ICE serial clock input (3V IO) ICE serial address/data input/output (3V IO) IOD0 or ICE serial clock input (for QFP64 package) IOD1 or ICE serial address/data input/output (for QFP64 package) IOD2 External reset IOD3 No Connection No Connection IOB0 or TPM channel 3 input/output F or motor drive W1N phase output IOB1 or TPM channel 3 input/output E or motor drive V1N phase output IOB2 or TPM channel 3 input/output D or motor drive U1N phase output IOB3 or TPM channel 3 input/output C or motor drive W1 phase output IOB4 or TPM channel 3 input/output B or motor drive V1 phase output IOB5 or TPM channel 3 input/output A or motor drive U1 phase output IOB6 or external fault protection input 1 IOB7 or overload protection input 1 IOB8 or TPM channel 0 input/output C IOB9 or TPM channel 0 input/output B IOB10 or TPM channel 0 input/output A IOB11 or SPI clock input/output IOB12 or SPI data input or UART receive data input 1 IOB13 or SPI data output or UART transmit data output 1 IOB14 IOB15 IOD12 IOD13 IOD14 IOD15 IOA8 IOA9 or TPM channel 2 input/output A IOA10 or TPM channel 2 input/output B IOA11 or external clock A input IOA12 or external clock B input IOA13 or external clock C input IOA14 or external clock D input IOA15 or A/D converter external trigger to start a conversion 5V power input for IO and built-in regulator Ground for IO 9 Feb. 16, 2006 Version: 1.1 Type Description
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PIN No Mnemonic QFP80 QFP64 IOA0/AN0 IOA1/AN1 IOA2/AN2 IOA3/AN3 IOA4/AN4 IOA5/AN5 IOA6/AN6 IOA7/AN7 VEXTREF AVSS AVDD VDDL XTAL1 XTAL2 VSSL IOD4 IOD5 IOD6 IOD7 IOD8 IOD9 IOD10 IOD11 NC IOC0/RXD2 IOC1/TXD2 IOC2/EXINT0 IOC3/EXINT1 IOC4/BZO IOC5/TIO1A IOC6/TIO1B IOC7/TIO1C IOC8/OL2 IOC9/FTIN2 IOC10/TIO4A/U2 IOC11/TIO4B/V2 IOC12/TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOC15/TIO4F/W2N 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Type
Description
I/O I/O I/O I/O I/O I/O I/O I/O I P P P I O P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
IOA0 or analog input channel 0 of ADC IOA1 or analog input channel 1 of ADC IOA2 or analog input channel 2 of ADC IOA3 or analog input channel 3 of ADC IOA4 or analog input channel 4 of ADC IOA5 or analog input channel 5 of ADC IOA6 or analog input channel 6 of ADC IOA7 or analog input channel 7 of ADC ADC top voltage reference Analog ground for ADC Analog power for ADC External capacitance pin for internal step-down regulator/Digital power External 3-6MHz crystal input for crystal oscillator External 3-6MHz crystal output / External clock input Digital ground IOD4 IOD5 IOD6 IOD7 IOD8 IOD9 IOD10 IOD11 No connection IOC0 or UART receive data input 2 IOC1 or UART transmit data output 2 IOC2 or external interrupt input 0 IOC3 or external interrupt input 1 IOC4 or buzzer output IOC5 or TPM channel 1 input/output A IOC6 or TPM channel 1 input/output B IOC7 or TPM channel 1 input/output C IOC8 or overload protection input 2 IOC9 or external fault input 2 IOC10 or TPM channel 4 input/output A or motor drive U2 phase output IOC11 or TPM channel 4 input/output B or motor drive V2 phase output IOC12 or TPM channel 4 input/output C or motor drive W2 phase output IOC13 or TPM channel 4 input/output E or motor drive U2N phase output IOC14 or TPM channel 4 input/output E or motor drive V2N phase output IOC15 or TPM channel 4 input/output F or motor drive W2N phase output
Legend: I = Input, O = Output, P = Power, PL = Pull-low, PH = Pull-high
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4.2. Pin Assignment 4.2.1. 80-Pin QFP Package
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
IOD11
IOD10
VSSL
XTAL2
XTAL1
VDDL
IOD9
IOD8
IOD7
IOD6
IOD5
IOD4
IOA6/AN6
IOA5/AN5
IOA4/AN4
IOA3/AN3
IOA2/AN2
IOA1/AN1
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
IOC0/RXD2 IOC1/TXD2 IOC2/EXINT0 IOC3/EXINT1 IOC4/BZO IOC5/TIO1A IOC6/TIO1B IOC7/TIO1C IOC8/OL2 IOC9/FTIN2 IOC10/TIO4A/U2 IOC11/TIO4B/V2 IOC12/TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOB13/SDO/TXD1 IOC15/TIO4F/W2N IOD1/ICESDA IOD0/ICECLK
VEXTREF
IOA7/AN7
IOA0/AN0
NC
AVDD
AVSS
VSS VDD IOA15/ADCTRG IOA14/TCLKD IOA13/TCLKC IOA12/TCLKB IOA11/TCLKA
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
QFP 80 - 14x20
IOA10/TIO2B IOA9/TIO2A IOA8 IOD15 IOD14 IOD13 IOD12 IOB15
IOB0/TIO3F/W1N
IOB2/TIO3D/U1N
IOB1/TIO3E/V1N
RESETB
ICESDA
ICECLK
ICEN
IOD2
IOD3
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
IOB12/SDI/RXD1
IOB14
IOB3/TIO3C/W1
IOB5/TIO3A/U1
IOB4/TIO3B/V1
IOB10/TIO0A
IOB8/TIO0C
IOB9/TIO0B
IOB6/FTIN1
IOB11/SCK
IOB7/OL1
23
24
Figure 4-1 SPMC75F2413A QFP80 package
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4.2.2. 64-Pin QFP Package
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
IOC2/EXINT0
IOC1/TXD2
IOD4
VSSL
XTAL2
IOC0/RXD2
XTAL1
IOA7/AN7
IOA6/AN6
IOA5/AN5
IOA4/AN4
IOA3/AN3
IOA2/AN2
IOA1/AN1
VEXTREF
IOA0/AN0
VDDL
AVDD
AVSS
52 53 54 55 56 57 58 59 60 61 62 63 64
IOC3/EXINT1 IOC4/BZO IOC5/TIO1A IOC6/TIO1B IOC7/TIO1C IOC8/OL2 IOC9/FTIN2 IOC10/TIO4A/U2 IOC11/TIO4B/V2 IOC12/TIO4C/W2 IOC13/TIO4D/U2N IOB0/TIO3F/W1N IOB2/TIO3D/U1N IOB3/TIO3C/W1 IOB5/TIO3A/U1 IOB4/TIO3B/V1 IOC14/TIO4E/V2N IOD1/ICESDA IOD0/ICECLK IOC15/ TIO4F /W3N IOB12/SDI/RXD1 IOB1/TIO3E/V1N
VSS VDD IOA15/ADCTRG IOA14/TCLKD IOA13/TCLKC
32 31 30 29 28 27 26 25 24 23 22 21 20
QFP 64 - 14x20
IOA12/TCLKB IOA11/TCLKA IOA10/TIO2B IOA9/TIO2A IOA8 IOB15 IOB14 IOB13/ SDO/ TXD1
IOB10/TIO0A 17
IOB8/TIO0C
IOB9/TIO0B
IOB6/FTIN1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IOB11/SCK 18
IOB7/OL1
RESETB
ICEN
IOD2
IOD3
19
Figure 4-2 SPMC75F2413A QFP64 package
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5. FUNCTIONAL DESCRIPTIONS
5.1. CPU Core
The SPMC75F2413A consists the newest 16-bit microprocessor,
5.2. Memory Organization 5.2.1. Memory Map
The device contains 32KW flash and 2KW SRAM. registers, and flash. data storage. peripheral modules. programming code. The memory space can be separated into three blocks: SRAM, I/O port The SRAM is used for stack, variable or The embedded flash is designed for The block diagram of memory is shown as The I/O port register is used to control the
'nSPTM (pronounced as micro-n-SP), developed by Sunplus
Innovation Technology. The CPU features include: 16-bit data bus / 22-bit address bus - 4M words (8M bytes) memory space - 64 banks / 64k words per bank Thirteen 16-bit registers - 5 general registers (R1-R5) - 4 secondary registers (SR1-SR4) - 3 system registers (SP, SR, PC) - Inner registers (FR) Ten interrupts - 1 fast interrupt (FIQ) - 8 normal interrupts (IRQ0-IRQ7) - 1 software interrupt (BRK) - Support IRQ nested mode Six addressing modes - Immediate (I6/I16) - Direct (A6/A16) - Indirect+ auto indexing address (DS indirect) - Relative (BP+IM6) - Multiple indirect (PUSH/POP) - Register 16x16 multiplication & up to 16-level inner product operation - Three multiplication mode: signed x signed, signed x unsigned, unsigned x unsigned - 4 bits guard bit of inner product operation to avoid overflow - Integer/Fraction mode 1-bit division - DIVS: divide the sign bit; DIVQ: divide the quotient - Divide 32-bit numerator and a 16-bit denominator Effective-exponent detect operation (EXP) Bit operation - Bit test / set / clr / inv operation to full memory space or registers Multi-cycles 16-bit shift operation - Support 32-bit shift with combining 2 shift instructions Far Indirect JMP by MR register Far Indirect Call by MR register NOP operation DS segment access instructions CPU inner flags access instructions
Figure 5-1. Table 5-1 shows the detailed memory allocation.
Memory Allocation 000000 0007FF
2K x 16 Working SRAM
. . .
007000
I/O Ports
007FFF 008000
Information 008000 Block 00803F
32K x 16 Embedded Flash
00FFFF
Figure 5-1 Memory allocation
Note: The address of 000800 - 006FFF and 010000 - 3FFFFF is reserved and cannot be accessed. An IAR (Illegal Address Reset) will be generated if CPU reads or writes these addresses. Table 5-1 Detailed Address Mapping I/O Address (Hex) Mapping 0000~07FF 2KW SRAM 0800~6FFF Illegal 7000~701F System Control 7020~704F Memory Control 7050~705F Reserved 7060~709F I/O Port Control 70A0~70AF Interrupt Control 70B0~70BF Time Base Control 70C0~70DF Timer Control 70E0~70FF Reserved 7100~711F UART Control 7120~713F Reserved 7140~715F SPI Control 7160~73FF Reserved 7400~747F Timer/PWM Module Control (for motor control) 7500~751F Compare Match Timer Control 7600~7FFF Illegal 8000~FFFF 32KW Program ROM 10000~ 3FFFFF Illegal
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5.2.2. Flash Organization and Control 5.2.2.1. Introduction
The SPMC75F2413A has two flash blocks: information block and normal block. the same time. Only one of the two blocks can be addressed at The information block contains 64 words. The The
0xFFFF 0x8000
16 Banks 2K x 16 : : : : : 2K x 16 2K x 16 2K x 16
Figure 5-3 Page0 and frame of flash
8 Frames 256 x16 256 x16 : : :
address of information block is mapped from 0x8000 ~ 0x803F. The 0x8000 is a system option register P_System_Option. version control, date, vender name, project name etc. other addresses are used for storing important information such The information block's structure is in Figure 5-2 and they only can be written in ICE mode or by writer. The 32K words of normal block are partitioned into 16 banks, 2K words each. Except the bank between 0xF000 and 0xF7FF can be programmed to be read-only or read-write in free run mode independently, the others are read-only bank. Moreover, each 2K-word bank can also be separated by eight frames so that the 32K embedded flash can be divided to 128 frames. separately.
Figure 5-3.
5.2.2.2. Flash Operation
There are two registers for flash control: P_Flash_RW (0x704D) and P_Flash_Cmd (0x7555). The flash access control, P_Flash_RW (0x704D), can be configured by two consecutive write cycles, keeping away from inadvertent writing. P_Flash_RW within 16 clock cycles. The flash command register, P_Flash_Cmd, is a write only register that is for accepting/performing flash command. Before performing any commands, users should write 0xAAAA to P_Flash_Cmd for entering flash command mode at first. Table 5-2 shows the command and access flow. First, write 0x5a5a to P_Flash_RW, and then write the configuration data to
The user can erase each frame
The relation of page and frame of flash is shown in
64 Words 0x8000 0x8001 : : : : 0x803F
Figure 5-2 Structure of Information block
P_System_Option
Remarkably, the characteristic of flash is that the data bit can only be programmed from 1 to 0, but it is not allowed to be from 0 to 1. Therefore, if users intend to program flash, the frame erase instruction must be executed first, which erase data bit from 0 to 1.
Example 6-1:
Set bank14 as read-only mode 0x5A5A (0x4000 >> 14) /* Flash Read Write Command */ //Flash RW Command
#define CW_FlashRW_CMD #define CB_BK14WDIS P_Flash_RW->W = CW_FlashRW_CMD;
P_Flash_RW->B.BK14WENB = CB_BK14WDIS; /* Set Bank 14 as Read Only */ Listing 6-1 read-only mode for bank 14 of flash memory
Table 5-2 Command function and access flow Frame Erase 1 cycle 2 cycle 3 cycle 4 cycle P_Flash_Cmd = 0xAAAA [ P_Flash_Cmd ] = 0x5511 Set Frame Address End Auto [ P_Flash_Cmd ] = 0x5533 Write Data [ P_Flash_Cmd ] = 0x5544 Write Data Wait 40us Go to 2 cycle [ P_Flash_Cmd ]= 0xFFFF Go to End Auto Program Mode Sequential Program Mode
Write any data and wait 20ms Wait 40us End Auto
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Example 6-2: Example for frame erasing: #define CW_FlashCMD #define CW_PageErase unsigned int *P_WordAdr; P_Flash_Cmd->W = CW_FlashCMD; P_Flash_Cmd->W = CW_PageErase; P_WordAdr = (unsigned int *)0xF000; *P_WordAdr = 0; /* P_WordAdr = start address of bank 14 */ /* Write any data to erase the first frame of bank 14 */ Listing 6-2 frame erasing of flash memory 0xAAAA 0x5511 //Flash Command FLash Block //Flash Page Erase Command
Example 6-3: Example for program mode: Write 0x1234 to the address of 0xF000 #define CW_FlashCMD #define CW_Program unsigned int *P_WordAdr; P_Flash_Cmd->W = CW_FlashCMD; P_Flash_Cmd->W = CW_Program; P_WordAdr = (unsigned int *)0xF000; *(unsigned int *)P_WordAdr = 0x1234; /* P_WordAdr = start address of bank 14 */ /* program one word = 0x1234 */ Listing 6-3 program mode of flash memory 0xAAAA 0x5533 //Flash Command FLash Block
//Flash Program Command
Example 6-4 Example for sequential program mode: Write data to flash with sequential program mode, address is from 0xF000 to 0xF020. #define CW_FlashCMD #define CW_Sequential #define CW_SequentialEnd unsigned int *P_WordAdr; unsigned int i,uiData=1; P_Flash_Cmd->W = CW_FlashCMD; for(i=0xF000;i<=0xF020;i++) { P_Flash_Cmd->W = CW_Sequential; P_WordAdr = (unsigned int *)i; *(unsigned int *)P_WordAdr = uiData; uiData ++; }/* End For Loop */ P_Flash_Cmd->W = CW_SequentialEnd; Listing 6-4 sequential program mode of flash memory // program address is the content of i // program uiData to P_WordAdr 0xAAAA 0x5544 0xFFFF //Flash Command FLash Block //Flash Sequential Program Command //Flash Sequential Program End Command
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* P_Flash_RW (0x704D): Embedded Flash Access Control Register The flash access control, P_Flash_RW, exclusively sets up banks14 with read only or full access in free run mode. This port can be configured by two consecutive write cycle to keep away B15 R 0 Reserved B7 R 1 Reserved B14 R/W 0 BK14WENB B6 R 1 Reserved B13 R 0 Reserved B5 R 1 Reserved B12 R 0 Reserved B4 R 1 Reserved from inadvertent writing. First, write 0x5A5A to P_Flash_RW, and then write configuration data to P_Flash_RW in duration of less than 16 clock cycles. B11 R 0 Reserved B3 R 1 Reserved B10 R 0 Reserved B2 R 1 Reserved B9 R 0 Reserved B1 R 1 Reserved B8 R 0 Reserved B0 R 1 Reserved
B15 B14 B13-0
Reserved BK14WENB Reserved F000h-F7FFh access control 0= Read/write 1= Read-only
* P_Flash_Cmd (0x7555): Embedded flash command register This port is used to issue flash command. B15 W 0 B14 W 0 Before performing any B12 W 0 FlashCmd B7 W 0 B6 W 0 B5 W 0 B4 W 0 FlashCmd * P_System_Option (0x8000): System Option Register B15 R/W 0 B14 R/W 1 B13 R/W 0 B12 R/W 1 B11 R/W 0 B10 R/W 1 B9 R/W 0 B8 R/W 1 B3 W 0 B2 W 0 B1 W 0 B0 W 0 entering flash command mode at first. Please see the Table 5-2. B11 W 0 B10 W 0 B9 W 0 B8 W 0 commands, users should write 0xAAAA to P_Flash_Cmd for B13 W 0
Verification Pattern B7 R/W 0 B6 R/W 1 Verification Pattern B5 R/W 0 B4 R/W 1 SCB B3 R/W 0 Reserved B2 R/W 1 LVR B1 R/W 1 WDG B0 R/W 1 CLKS
B15-5 B4
Verification Pattern SCB
ICE or Writer will write 01010101010 to this area Security enable, active low 0: Security enabled, the 1: Security disabled, can be normal block in the flash readable or write-able cannot be accessed
B3 B2 B1
Reserved LVR WDG Enable low voltage reset function Enable watchdog function 16 0: Disable 0: Disable 1: Enable 1: Enable Feb. 16, 2006 Version: 1.1
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B0
CLKS
Clock Source Selection
0:
external
clock
input, 1: crystal oscillator, connect a device between XTAL1 and XTAL2.
connect an oscillator or clock crystal source to XTAL2.
The "mass erase" command execute on main block is to erase main block only, but erase main block and information block if the command execute on information block. In case of security option in information block is enabled, SPMC75F2413A are protected from reading data through ICE or Writer function. If the security
Table 5-3 Flash/SRAM access table in normal and ICE mode Normal mode(ICEN=0) SCB =0 Read SRAM FLASH main block FLASH information block ICE mode(ICEN=1) SRAM FLASH main block FLASH information block No No No No No (but mass erase) No (but mass erase) Yes Yes Yes Yes Yes Yes Yes Yes Yes Write Yes Yes No SCB =1 Read Write Yes Yes Yes Yes Yes No
is enabled on under ICE enable mode, the flash main block does not allow to be read/write but information block can be read by ICE and the only command that user can perform is "mass erase". mode. Please refer to Table 5-3 for detail. In normal operation (ICEN = 0), CPU can access the flash data and the working SRAM. The ICE cannot program the flash memory when the ICE mode is activated and security is enabled. This hardware protection prevents hackers from downloading a program to flash or SRAM then write source code out to GPIOs. Table 5-3 shows Flash and SRAM access table. In addition, SRAM cannot be accessed (read/write) in ICE enable
5.2.2.3. Power-up procedure
When power is turned on, option bits are read by the system. The option bits are stored in the first word of embedded flash information block (address = 0x8000). When power is turned on, the system reset is activated until the power-on-timer counts 16384 cycles of 200KHz clock then, reset signal is released. Remarkably, all GPIO is on the high impedance state initially and can be configured after power-on procedure.
16384 cycles of clock (82ms) 200KHz clock System clock Power-on reset CPU address System reset All GPIO go to Hi-Z state All GPIO Configure GPIO FFF7
Figure 5-4 Power-up procedure
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5.2.3. SRAM
The SRAM can be used for stack, variable and data storage. Stack is used for storing the return address of function call and pushing instruction data. The direction of stack goes from bottom to up. This stack is a FILO (first in last out) structure, and the stack address is indicated by stack pointer (SP). The variable and data storage is configured by the user. or save SRAM data. unknown state. 2K-word SRAM. Users
5.2.4. Reset and Interrupt Vectors
Addresses 0xFFF5 to 0xFFFF are reserved for reset and interrupt vectors. A reset forces the program counter (PC) points to When a device reset occurs, the program The address and address 0xFFF7.
execution will branch to 0xFFF7, named "Reset Vector Address". The SPMC75F2413A has 10 interrupts. function name list are given in the following table.
can use direct access, indirect access or base pointer (BP) to load Note that the stack and variable or storage data must not overlap each other; otherwise, CPU will run into an The SPMC75F2413A addresses maximum The address range is from 0x0000 to 0x07FF.
Table 5-4 Interrupts vectors list Reset or IRQ vector BRK FIQ Reset IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Address 0xFFF5 0xFFF6 0xFFF7 0xFFF8 0xFFF9 0xFFFA 0xFFFB 0xFFFC 0xFFFD 0xFFFE 0xFFFF
In addition, the stack pointer (SP) is allocated at the end of maximum address initially, i.e. 0x07FF.
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CPU and Peripherals Control Registers List * CPU control/status registers Register Name Reset value Bit Field R/W B15 B7 0x7006-7555: CPU control/status registers 0x7006 P_Reset_Status 0x0000 R IIRF IARF LVRF WDRF PORF EXTRF B14 B6 B13 B5 B12 B4 B11 B3 B10 B2 B9 B1 B8 B0
Address
The flag of reset status for firmware checking. W IIRF IARF LVRF WDRF PORF EXTRF
To properly clear reset flags, FCHK must be written to 0x55 with specified reset flag is set to 1. 0x7007 P_Clk_Ctrl 0x0000 R OSCSF OSCIE This register is used for monitoring CPU clock status W OSCSF OSCIE Write `1' to OSCSF will clear this flag. 0x700A P_WatchDog_Ctrl 0x0000 R WDEN WDRS WDCHK WDPS
This register provides the watchdog clear timer and on/off function for firmware setting W WDEN WDRS WDCHK WDPS
To change the settings of this register, WDCHK must be written with "10101". 0x700B P_WatchDog_Clr 0x0000 R Watchdog Clear Register Watchdog Clear Register This register is used to clear watchdog timer, Write 0xA005 to clear watchdog timer 0x700C P_Wait_Enter 0x0000 R Wait-Mode Entrance Register Wait-Mode Entrance Register Read 0x0001 indicates that it is wake-up from wait mode. W Wait-Mode Entrance Register Wait-Mode Entrance Register Write 0x5005 to enter wait mode (CPU off, PLL on) and write 0x0001 will clear wait flag. 0x700E P_Stdby_Enter 0x0000 R Standby-Enter Entrance Register Standby-Enter Entrance Register Read 0x0001 indicates that it is wake-up from Standby mode. W Standby-Enter Entrance Register Standby-Enter Entrance Register Write 0xA00A to enter standby mode (CPU off, PLL off) and write 0x0001 will clear standby flag. 0x700F P_Wakeup_Ctrl 0x0000 R/W KEYWE UARTWE SPIWE EXT1WE EXT0WE
TPM2WE PDC1WE PDC0WE CMTWE
This register determines the wakeup source when the chip is in power-saving mode. 0x704D P_Flash_RW 0x0000 R/W BK14WNB (c) Sunplus Innovation Technology Inc. Proprietary & Confidential 19 Feb. 16, 2006 Version: 1.1
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Address
Register Name
Reset value
Bit Field R/W B15 B7 B14 B6 B13 B5 B12 B4 B11 B3 B10 B2 B9 B1 B8 B0
First, write 0x5A5A to P_Flash_RW, and then write configuration data to P_Flash_RW in duration of less than 16 clock cycles. 0x7555 P_Flash_Cmd 0x0000 R/W Embedded Flash Access Control Register Embedded Flash Access Control Register This port is used to issue flash command. * IO Port registers Register Name Reset value Bit Field R/W B15 B7 0x7060-0x7084: CPU control/status registers 0x7060 P_IOA_Data 0x0000 R IO Port A Data Register IO Port A Data Register Read data from the I/O pad W IO Port A Data Register IO Port A Data Register Write data into the data register and read data from the I/O pad 0x7061 P_IOA_Buffer 0x0000 R IO Port A Buffer Register IO Port A Buffer Register Read data from the I/O buffer W IO Port A Buffer Register IO Port A Buffer Register Write data into the data register and read data from the I/O pad 0x7062 P_IOA_Dir 0x0000 R/W IO Port A Direction Register IO Port A Direction Register Direction-vector from/into the direction register 0x7063 P_IOA_Attrib 0xFFFF R/W IO Port A Attrib Register IO Port A Attrib Register The attribute setting gives a feature to the pin, float / pull for input, not inverted/ inverted for output 0x7064 P_IOA_Latch 0x0000 R IO Port A Latch Register IO Port A Latch Register Read this port to latch data on the I/O PortA for key change wakeup before getting into sleep mode 0x7068 P_IOB_Data 0x0000 R IO Port B Data Register IO Port B Data Register Read data from the I/O pad W IO Port B Data Register IO Port B Data Register Write data into the data register and read data from the I/O pad 0x7069 P_IOB_Buffer 0x000 R IO Port B Buffer Register IO Port B Buffer Register Read data from the I/O buffer (c) Sunplus Innovation Technology Inc. Proprietary & Confidential 20 Feb. 16, 2006 Version: 1.1 B14 B6 B13 B5 B12 B4 B11 B3 B10 B2 B9 B1 B8 B0
Address
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Address
Register Name
Reset value
Bit Field R/W B15 B7 W B14 B6 B13 B5 B12 B4 B11 B3 B10 B2 B9 B1 B8 B0
IO Port B Buffer Register IO Port B Buffer Register Write data into the data register and read data from the I/O pad
0x706A
P_IOB_Dir
0x0000
R/W
IO Port B Direction Register IO Port B Direction Register Direction-vector from/into the direction register
0x706B
P_IOB_Attrib
0xFFFF R/W
IO Port B Attrib Register IO Port B Attrib Register The attribute setting gives a feature to the pin, float / pull for input, not inverted/ inverted for output
0x7070
P_IOC_Data
0x000
R
IO Port C Data Register IO Port C Data Register Read data from the I/O pad
W
IO Port C Data Register IO Port C Data Register Write data into the data register and read data from the I/O pad
0x7071
P_IOC_Buffer
0x000
R
IO Port C Buffer Register IO Port C Buffer Register Read data from the I/O buffer
W
IO Port C Buffer Register IO Port C Buffer Register Write data into the data register and read data from the I/O pad
0x7072
P_IOC_Dir
0x000
R/W
IO Port C Direction Register IO Port C Direction Register Direction-vector from/into the direction register
0x7073
P_IOC_Attrib
0xFFFF R/W
IO Port C Attrib Register IO Port C Attrib Register The attribute setting gives a feature to the pin, float / pull for input, not inverted/ inverted for output
0x7078
P_IOD_Data
0x000
R
IO Port D Data Register IO Port D Data Register Read data from the I/O pad
W
IO Port D Data Register IO Port D Data Register Write data into the data register and read data from the I/O pad
0x7079
P_IOD_Buffer
0x000
R
IO Port D Buffer Register IO Port D Buffer Register Read data from the I/O buffer
W
IO Port D Buffer Register IO Port D Buffer Register Write data into the data register and read data from the I/O pad
0x707A
P_IOD_Dir
0x000
R/W
IO Port D Direction Register IO Port D Direction Register
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Address
Register Name
Reset value
Bit Field R/W B15 B7 B14 B6 B13 B5 B12 B4 B11 B3 B10 B2 B9 B1 B8 B0
Direction-vector from/into the direction register 0x707B P_IOD_Attrib 0xFFFF R/W IO Port D Attrib Register IO Port D Attrib Register The attribute setting gives a feature to the pin, float / pull for input, not inverted/ inverted for output 0x7080 P_IOA_SPE 0x0000 R/W TCLKDEN TCLKCEN TCLKBEN TCLKAEN TIO2BEN TIO2AEN PortA special function enable register 0x7081 P_IOB_SPE 0x003F R/W OL1EN FTIN1EN U1EN V1EN W1EN TIO0AEN TIO0BEN TIO0AEN U1NEN V1NEN W1NEN
PortB special function enable register 0x7082 P_IOC_SPE 0xFC00 R/W W2NEN V2NEN U2NEN W2EN V2EN U2EN FTIN2EN OL2EN
TIO1CEN TIO1BEN TIO1AEN
EXINT1EN EXINT0EN
PortC special function enable register 0x7084 P_IOA_KCER 0x000 R/W KC15EN KC14EN KC13EN KC12EN KC11EN PortA key-change pin enable register KC10EN KC9EN KC8EN
Address
Function
Reset value 0x0000
Bit Field R/W B15 B7 B14 B6 UARTIF PDC1IF B13 B5 SPIIF PDC0IF B12 B4 EXT1IF CMTIF B11 B3 EXT0IF B10 B2 ADCIF OLIF B9 B1 MCP4IF OSCSF B8 B0 MCP3IF FTIF
0x70A0
P_INT_Status
R/W
KEYIF TPM2IF
Only the KEYIF, EXT0IF and EXT1IF can write `1' to clear these flags. Other status flags are and read only. 0x70A4 P_INT_Priority 0x0000 R/W KEYIP TPM2IP UARTIP PDC1IP SPIIP PDC0IP CMTIP EXTIP ADCIP OLIP MCP4IP OSCIP MCP3IP FTIP
Set interrupt source as IRQ or FIQ. Only one of interrupt source can be set as FIQ 0x70A8 P_MisINT_Ctrl 0x0000 R/W KEYIE EXT1MS EXT0MS EXT1IE Miscellaneous setting for key-change and external input interrupt enable 0x70B8 P_TMB_Reset 0x0000 W Time Base Reset Register Time Base Reset Register Write 0x5555h to this register to reset the time base counter register to initial the clock sources of all peripherals on the chip 0x70B9 P_BZO_Ctrl 0x000 R/W BZOEN Buzzer output frequency selection and output enable BZOCK EXT0IE
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* ADC control/status registers Register Name P_ADC_Setup Reset value 0x0000 Bit Field R/W B15 B7 0x7160 R/W ADCCS ASPEN trigger the start operation of ADC 0x7161 P_ADC_Ctrl 0x0000 R/W ADCIF ADCIE ADCCHS B14 B6 ADCEN B13 B5 B12 B4 B11 B3 B10 B2 ADCFS B9 B1 B8 B0 ADC EXTRG
Address
Control the ADC block power on or off, ADC conversion clock and event selection to
ADCRDY ADCSTR selection 0x70A2 P_ADC_Channel 0x0000 R/W
ADC interrupt enable on/off, manually start ADC conversion and ADC convert channels ADCCH7 ADCCH6 ADCCH5 ADCCH4 ADCCH3 ADCCH2 ADCCH1 ADCCH0 Configures the IOA[7:2] is either GPIO port or analog input port 0x7162 P_ADC_Data 0xFFC0 R ADCDATA 10-bits ADC conversion result register * UART and SPI control/status registers Reset value 0x0000 Bit Field R/W B15 B7 0x7100 P_UART_Data R B14 B6 B13 B5 B12 B4 B11 B3 OE UARTDATA Data register for UART reception. This register also indicates the error flags during reception. W UARTDATA Data register for UART transmission 0x7101 P_UART_RXStatus 0x0000 R OE PE FE B10 B2 B9 B1 PE B8 B0 FE ADCDATA
Address
Function
This register indicates the error flags during reception 0x7102 P_UART_Ctrl 0x000 R/W RXIE TXIE RXEN TXEN Reset SBSEL TXCHSEL RXCHSEL PSEL PEN
Control the setting for UART receive/transmit pin enable, stop bit, and parity selection 0x7103 P_UART_BaudRate 0x000 R/W UART Baud Rate Setup Register UART Baud Rate Setup Register This register determines the baud-rate of UART 0x7104 P_UART_Status 0x000 R RXIF TXIF RXBF BY
UART reception and transmission status flags 0x7140 P_SPI_Ctrl 0x0000 R/W SPIE SPIPHA SPIPOL SPIRST SPISMPS SPISPCLK SPIFS SPIMS
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Address
Function
Reset value 0x000
Bit Field R/W B15 B7 B14 B6 B13 B5 SPITXBF SPI transmission interrupt enable and status flags B12 B4 B11 B3 B10 B2 B9 B1 B8 B0
0x7141
P_SPI_TxStatus
R
SPITXIF SPITXIE
0x7142
P_SPI_TxBuf
0x0000
R/W
SPITXBUF SPI transmission buffer register
0x7143
P_SPI_RxStatus
0x0000
R/W SPIRXIF SPIRXIE

FERR
SPI reception interrupt enable and status flags 0x7144 P_SPI_RxBuf 0x000 R/W SPIRXBUF SPI reception buffer register * PDC0/1 Timers control/status registers Reset value 0x0000 Bit Field R/W B15 B7 0x7405 P_TMR_Start R/W TMR4ST B14 B6 B13 B5 B12 B4 TMR3ST TMR2ST TMR1ST TMR0ST B11 B3 B10 B2 B9 B1 B8 B0
Address
Function
PDC0/1, TPM2, and MCP3/4 timers start or stop control register 0x7400 P_TMR0_Ctrl 0x0000 R/W SPCK CCLS MODE CKEGS CLEGS TMRPS
Configures the selection of timer clock source, counter clock edge, counter clear source, counter clear edge, capture input sample clock and timer operating modes 0x7401 P_TMR1_Ctrl 0x0000 R/W SPCK CCLS MODE CKEGS CLEGS TMRPS
Configures the selection of timer clock source, counter clock edge, counter clear source, counter clear edge, capture input sample clock and timer operating modes 0x7410 P_TMR0_IOCtrl 0x0000 R/W IOBMODE TIO0A, TIO0B, and TIO0C pins 0x7411 P_TMR1_IOCtrl 0x0000 R IOBMODE TIO1A, TIO1B, and TIO1C pins 0x7420 P_TMR0_INT 0x0000 R/W TADSE TCUIE TCVIE TPRIE TGCIE TGBIE PDCIE TGAIE IOCMODE IOAMODE IOCMODE IOAMODE
Controls the PWM output, input capture, and position detection change action type of
Controls the PWM output, input capture, and position detection change action type of
Enable or disable A/D conversion start request by TGRA compare match, interrupt requests for position detection changes, overflow/underflow of TCNT, period register compare match and input capture/compare match of TGRA, TGRB, TGRC 0x7421 P_TMR1_INT 0x000 R/W TADSE (c) Sunplus Innovation Technology Inc. Proprietary & Confidential TCUIE 24 TCVIE TPRIE TGCIE TGBIE PDCIE TGAIE
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Address
Function
Reset value
Bit Field R/W B15 B7 B14 B6 B13 B5 B12 B4 B11 B3 B10 B2 B9 B1 B8 B0
Enable or disable A/D conversion start request by TGRA compare match, interrupt requests for position detection changes, overflow/underflow of TCNT, period register compare match and input capture/compare match of TGRA, TGRB, TGRC 0x7425 P_TMR0_Status 0x000 R/W TCDF TCUIF TCVIF TPRIF TGCIF TGBIF PDCIF TGAIF
Indicates the event generation of position detection changes, an underflow/overflow of TCNT, period register compare match and input capture/compare match of TGRA, TGRB, TGRC 0x7426 P_TMR1_Status 0x000 R/W TCDF TCUIF TCVIF TPRIF TGCIF TGBIF PDCIF TGAIF
Indicates the event generation of position detection changes, an underflow/overflow of TCNT, period register compare match and input capture/compare match of TGRA, TGRB, TGRC 0x7462 P_POS0_DectCtrl 0x0000 R/W SPLCK PDEN TIO0C input pins. 0x7463 P_POS1_DectCtrl 0x0000 R/W SPLCK PDEN TIO1C input pins. 0x7464 P_POS0_DectData 0x0000 R The current filtered position data will be latched to this register 0x7465 P_POS1_DectData 0x000 R The current filtered position data will be latched to this register 0x7430 P_TMR0_TCNT 0x000 R Timer 0 Counter Register Timer 0 Counter Register The 16-bit readable registers that increment/decrement according to input clocks 0x7431 P_TMR1_TCNT 0x000 R Timer 1 Counter Register Timer 1 Counter Register The 16-bit readable registers that increment/decrement according to input clocks 0x7440 P_TMR0_TGRA 0x0000 R/W Timer 0 General Register A Timer 0 General Register A The 16-bit register, functioning as either PWM output or input capture register 0x7441 P_TMR0_TGRB 0x0000 R/W Timer 0 General Register B Timer 0 General Register B The 16-bit register, functioning as either PWM output or input capture register 0x7442 P_TMR0_TGRC 0x0000 R Timer 0 General Register C Timer 0 General Register C The 16-bit register, functioning as either PWM output or input capture register 0x7433 P_TMR1_TGRA 0x0000 R/W 25 Timer 1 General Register A Feb. 16, 2006 Version: 1.1 PDR PDR SPLMOD SPDLY SPLCNT SPLMOD SPDLY SPLCNT
Control the sampling settings of position detection signals from TIO0A, TIO0B and
Control the sampling settings of position detection signals from TIO1A, TIO1B and
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Address
Function
Reset value
Bit Field R/W B15 B7 B14 B6 B13 B5 B12 B4 B11 B3 B10 B2 B9 B1 B8 B0
Timer 1 General Register A The 16-bit register, functioning as either PWM output or input capture register 0x7444 P_TMR1_TGRB 0x0000 R/W Timer 1 General Register B Timer 1 General Register B
0x7445
P_TMR1_TGRC
0x0000
R/W
Timer 1 General Register C Timer 1 General Register C The 16-bit register, functioning as either PWM output or input capture register
0x7450
P_TMR0_TBRA
0x0000
R
Timer 0 Buffer Register A Timer 0 Buffer Register A The timer buffer register is the double buffer for TGRA. When used as input capture function, the TCNT value is stored at the falling edge of input capture port.
0x7451
P_TMR0_TBRB
0x000
R
Timer 0 Buffer Register B Timer 0 Buffer Register B The timer buffer register is the double buffer for TGRB. When used as input capture function, the TCNT value is stored at the falling edge of input capture port.
0x7452
P_TMR0_TBRC
0x000
R
Timer 0 Buffer Register C Timer 0 Buffer Register C The timer buffer register is the double buffer for TGRC. When used as input capture function, the TCNT value is stored at the falling edge of input capture port.
0x7453
P_TMR1_TBRA
0x0000
R
Timer 1 Buffer Register A Timer 1 Buffer Register A The timer buffer register is the double buffer for TGRA. When used as input capture function, the TCNT value is stored at the falling edge of input capture port.
0x7454
P_TMR1_TBRB
0x000
R
Timer 1 Buffer Register B Timer 1 Buffer Register B The timer buffer register is the double buffer for TGRB. When used as input capture function, the TCNT value is stored at the falling edge of input capture port.
0x7455
P_TMR1_TBRC
0x000
R
Timer 1 Buffer Register C Timer 1 Buffer Register C The timer buffer register is the double buffer for TGRC. When used as input capture function, the TCNT value is stored at the falling edge of input capture port.
0x7435
P_TMR0_TPR
0xFFFF
R/W
Timer 0 Period Register Timer 0 Period Register The 16-bit readable/writable register. It is used to setup the period interrupt of timer.
0x7436
P_TMR1_TPR
0xFFFF
R/W
Timer 1 Period Register Timer 1 Period Register The 16-bit readable/writable register. It is used to setup the period interrupt of timer.
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* TPM2 Timers control/status registers Register Name P_TMR2_Ctrl Reset value 0x0000 Bit Field R/W B15 B7 0x7402 R/W SPCK CCLS B14 B6 B13 B5 B12 B4 MODE CKEGS B11 B3 B10 B2 B9 B1 CLEGS TMRPS B8 B0
Address
Configures the selection of timer clock source, counter clock edge, counter clear source, counter clear edge, capture input sample clock and timer operating modes 0x7412 P_TMR2_IOCtrl 0x0000 R/W IOBMODE IOAMODE
Controls the PWM output and input capture action type of TIO2A, and TIO2B pins 0x7422 P_TMR2_INT 0x0000 R/W TADSE TPRIE TGBIE TGAIE
Enable or disable A/D conversion start request by TGRA compare match, interrupt requests for period register compare match and input capture/compare match of TGRA or TGRB. 0x7427 P_TMR2_Status 0x0000 R/W TCDF TPRIF TGBIF TGAIF
Indicates the event generation of a period registers compare match and input capture/compare match of TGRA or TGRB 0x7432 P_TMR2_TCNT 0x0000 R Timer 2 Counter Register Timer 2 Counter Register The 16-bit readable registers that increment/decrement according to input clocks 0x7446 P_TMR2_TGRA 0x0000 R/W Timer 2 General Register A Timer 2 General Register A The 16-bit register, functioning as either PWM output or input capture register 0x7447 P_TMR2_TGRB 0x0000 R/W Timer 2 General Register B Timer 2 General Register B The 16-bit register, functioning as either PWM output or input capture register 0x7456 P_TMR2_TBRA 0x0000 R Timer 2 Buffer Register A Timer 2 Buffer Register A The timer buffer register is the double buffer for TGRA. When used as input capture function, the TCNT value is stored at the falling edge of input capture port. 0x7457 P_TMR2_TBRB 0x0000 R Timer 2 Buffer Register B Timer 2 Buffer Register B The timer buffer register is the double buffer for TGRB. When used as input capture function, the TCNT value is stored at the falling edge of input capture port. 0x7437 P_TMR2_TPR 0xFFFF R/W Timer 2 Period Register Timer 2 Period Register The 16-bit readable/writable register. It is used to setup the period interrupt of timer.
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* MCP 3/4 Timers control/status registers Register Name P_TPWM_Write Reset value 0x000 Bit Field R/W B15 B7 0x7409 R/W B14 B6 B13 B5 B12 B4 TMR4WE TMR3WE B11 B3 B10 B2 B9 B1 B8 B0
Address
Write 0x5A01 and 0x5A03 to this register to enable timer 3 or 4 for timer PWM generation. 0x740A P_TMR_LDOK 0x000 R/W TLDCHK To correctly set the LDOK bits, the pattern `101010' must be written to. 0x7403 P_TMR3_Ctrl 0x0000 R/W PRDINT CCLS MODE CKEGS TMRPS LDOK1 LDOK0
Configures the selection of timer clock source, counter clock edge, counter clear source, TPR interrupt frequency and timer operating modes. 0x7404 P_TMR4_Ctrl 0x000 R/W PRDINT CCLS MODE CKEGS TMRPS
Configures the selection of timer clock source, counter clock edge, counter clear source, TPR interrupt frequency and timer operating modes. 0x7413 P_TMR3_IOCtrl 0x0000 R/W IOBMODE IOCMODE IOAMODE
Controls the PWM compare match output action type of TIO3A, TIO3B, and TIO3C pins. 0x7414 P_TMR4_IOCtrl 0x0000 R/W IOBMODE IOCMODE IOAMODE
Controls the PWM compare match output action type of TIO4A, TIO4B, and TIO4C pins. 0x7423 P_TMR3_INT 0x000 R/W TADSE TPRIE TGDIE
Enable or disable A/D conversion start request by TGRD compare match, interrupt requests for period register compare match and compare match of TGRD. 0x7424 P_TMR4_INT 0x0000 R/W TADSE TPRIE TGDIE
Enable or disable A/D conversion start request by TGRD compare match, interrupt requests for period register compare match and compare match of TGRD. 0x7428 P_TMR3_Status 0x000 R/W TCDF TPRIF TGDIF
Indicates the event generation of period register compare match and compare match of TGRD. These flags show the interrupt sources. 0x7429 P_TMR4_Status 0x000 R/W TCDF TPRIF TGDIF
Indicates the event generation of period register compare match and compare match of TGRD. These flags show the interrupt sources. 0x7428 P_TMR_Output 0x0000 R/W TMR4FOE TMR4EOE TMR4DOE TMR4COE TMR4BOE TMR4AOE TMR3FOE TMR3EOE TMR3DOETMR3COE TMR3BOE TMR3AOE
Enables/disables the PWM outputs of MCP3/4 timer module. The PWM output will be high-impedance if disabled. 0x7407 P_TMR3_OutputCtrl 0x000 R/W DUTY MODE POLP WPWM VPWM
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Address
Register Name
Reset value
Bit Field R/W B15 B7 UPWM B14 B6 SYNC B13 B5 WOC B12 B4 B11 B3 VOC B10 B2 B9 B1 UOC B8 B0
Setting for the PWM waveform output type of MCP3 timer. 0x7408 P_TMR4_OutputCtrl 0x0000 R/W DUTY MODE UPWM POLP SYNC WOC VOC WPWM VPWM
UOC
Setting for the PWM waveform output type of MCP4 timer. 0x7460 P_TMR3_DeadTime 0x0000 R/W Dead time setting for MCP3 timer outputs. 0x7461 P_TMR4_DeadTime 0x000 R/W Dead time setting for MCP4 timer outputs. 0x7466 P_Fault1_Ctrl 0x0000 R/W OCE FTPINE OCIE FTPINIE OCLS FTPINIF OSF FTCNT DTWE DTVE DTUE DTP DTWE DTVE DTUE DTP
Fault control configuration settings for FTIN1. 0x7467 P_Fault2_Ctrl 0x000 R/W OCE FTPINE OCIE FTPINIE OCLS FTPINIF OSF FTCNT
Fault control configuration settings for FTIN2. 0x746A P_Fault1_Release 0x000 R/W Fault 1 Flag Release Register Fault 1 Flag Release Register 1. Write 0x55AA then 0xAA55 sequentially to clear FTPINIF flag in P_Fault1_Ctrl register. 2. Write 0xAA55 then 0x55AA sequentially to clear OSCSF flag in P_Fault1_Ctrl register. 0x746B P_Fault2_Release 0x0000 R/W Fault 2 Flag Release Register Fault 2 Flag Release Register 1. Write 0x55AA then 0xAA55 sequentially to clear FTPINIF flag in P_Fault2_Ctrl register. 2. Write 0xAA55 then 0x55AA sequentially to clear OSCSF flag in P_Fault2_Ctrl register. 0x7468 P_OL1_Ctrl 0x000 R/W OLEN OLIE CNTSP OLIF OLMD OLST RTTMB RTPWM RTOL
OLCNT
Overload control configuration settings for OL1. 0x7469 P_OL2_Ctrl 0x000 R/W OLEN OLIE CNTSP OLIF OLMD OLST RTTMB RTPWM RTOL
OLCNT
Overload control configuration settings for OL2. 0x7433 P_TMR3_TCNT 0x0000 R Timer 3 Counter Register Timer 3 Counter Register The 16-bit readable registers that increment/decrement according to input clocks 0x7434 P_TMR4_TCNT 0x000 R Timer 4 Counter Register Timer 4 Counter Register The 16-bit readable registers that increment/decrement according to input clocks 0x7448 P_TMR3_TGRA 0x0000 R/W Timer 3 General Register A Timer 3 General Register A The 16-bit readable/writable registers, functioning as PWM duty for TIO3A/TIO3D. 0x7449 P_TMR3_TGRB 0x0000 R/W Timer 3 General Register B Timer 3 General Register B (c) Sunplus Innovation Technology Inc. Proprietary & Confidential 29 Feb. 16, 2006 Version: 1.1
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Address
Register Name
Reset value
Bit Field R/W B15 B7 B14 B6 B13 B5 B12 B4 B11 B3 B10 B2 B9 B1 B8 B0
The 16-bit readable/writable registers, functioning as PWM duty for TIO3B/TIO3E. 0x744A P_TMR3_TGRC 0x000 R/W Timer 3 General Register C Timer 3 General Register C The 16-bit readable/writable registers, functioning as PWM duty for TIO4C/TIO4F. 0x744B P_TMR3_TGRD 0x000 R/W Timer 3 General Register D Timer 3 General Register D Used as the ADC conversion start signal when TCNT counter value match this register content or general compare match register. 0x744C P_TMR4_TGRA 0x000 R/W Timer 4 General Register A Timer 4 General Register A The 16-bit readable/writable registers, functioning as PWM duty for TIO4A/TIO4D. 0x744D P_TMR4_TGRB 0x000 R/W Timer 4 General Register B Timer 4 General Register B The 16-bit readable/writable registers, functioning as PWM duty for TIO4B/TIO4E. 0x744E P_TMR4_TGRC 0x000 R/W Timer 4 General Register C Timer 4 General Register C The 16-bit readable/writable registers, functioning as PWM duty for TIO4C/TIO4F. 0x744F P_TMR4_TGRD 0x000 R/W Timer 4 General Register D Timer 4 General Register D Used as the ADC conversion start signal when TCNT counter value match this register content or general compare match register. 0x7458 P_TMR3_TBRA 0x000 R Timer 3 Buffer Register A Timer 3 Buffer Register A The timer buffer register is the double buffer for TGRA. 0x7459 P_TMR3_TBRB 0x0000 R Timer 3 Buffer Register B Timer 3 Buffer Register B The timer buffer register is the double buffer for TGRB. 0x745A P_TMR3_TBRC 0x000 R Timer 3 Buffer Register C Timer 3 Buffer Register C The timer buffer register is the double buffer for TGRC. 0x745C P_TMR4_TBRA 0x000 R Timer 4 Buffer Register A Timer 4 Buffer Register A The timer buffer register is the double buffer for TGRA. 0x745D P_TMR4_TBRB 0x000 R Timer 4 Buffer Register B Timer 4 Buffer Register B The timer buffer register is the double buffer for TGRB. 0x745E P_TMR4_TBRC 0x000 R Timer 4 Buffer Register C Timer 4 Buffer Register C The timer buffer register is the double buffer for TGRC. 0x7438 P_TMR3_TPR 0xFFFF R/W Timer 3 Period Register Timer 3 Period Register The 16-bit readable/writable register. 0x7439 P_TMR4_TPR 0xFFFF R/W 30 It is used to setup the period interrupt of timer.
Timer 4 Period Register Feb. 16, 2006 Version: 1.1
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Address
Register Name
Reset value
Bit Field R/W B15 B7 B14 B6 B13 B5 B12 B4 B11 B3 B10 B2 B9 B1 B8 B0
Timer 4 Period Register The 16-bit readable/writable register. * CMT timer control/status registers Register Name P_CMT_Start Reset value 0x0000 Bit Field R/W B15 B7 0x7500 R/W CMT01 and CMT1 timers start or stop control register 0x7501 P_CMT_Ctrl 0x000 R/W CM1IF CM0IF CM1IE CM0IE CKB CKA B14 B6 B13 B5 B12 B4 ST1 ST0 B11 B3 B10 B2 B9 B1 B8 B0 It is used to setup the period interrupt of timer.
Address
CMT0 and CMT1 timers interrupt enable and clock selection register. 0x7508 P_CMT0_TCNT 0x000 R Compare Match Timer 0 Counter Register Compare Match Timer 0 Counter Register The 16-bit readable registers that increment/decrement according to input clocks 0x7509 P_CMT1_TCNT 0x000 R Compare Match Timer 1 Counter Register Compare Match Timer 1 Counter Register The 16-bit readable registers that increment/decrement according to input clocks 0x7510 P_CMT0_TPR 0xFFFF R/W Compare Match Timer 0 Period Register Compare Match Timer 0 Period Register The 16-bit readable/writable register. 0x7511 P_CMT1_TPR 0xFFFF R/W It is used to setup the period interrupt of timer.
Compare Match Timer 1 Period Register Compare Match Timer 1 Period Register The 16-bit readable/writable register. It is used to setup the period interrupt of timer.
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5.3. Clock Generation Module (CGM)
The Clock Generation Module generates all the clock sources needed for system operation. It contains a crystal oscillator, PLL (Phase-Lock-Loop) circuit, external clock and clock monitoring circuit. Additionally, the built-in RC oscillator is dedicated to Power-on timer and flash control for writing operation.
From Crystal Pad External Clock P_System_Option.CLKS
Figure 5-6 PLL and external clock block diagram
3 ~ 6MHz Crystal
PLL X 4
12 ~ 24MHz Clock 1 0
System Clock
5.3.1. Crystal Oscillator
The crystal oscillator uses crystal device for clock generation. The range is between 3M ~ 6MHz. The oscillator output will be used as PLL clock source and the PLL circuit pumps the input clock to four times. Thus, if the 6MHz crystal is connected, the PLL output clock will be pumped to 24MHz.
5.3.3. External clock
The CLKS in P_System_Option can configure an external clock between 12MHz and 24MHz as the clock source. Figure 5-7 shows the connection of external clock from oscillator.
3~6MHz Crystal Oscillator
C1 20p
+5V
XTAL1 Y2 3~6MHz XTAL2
1 Y1 OSC NC VCC 4
SPMC75F2413A
C 0.1uF 2
SPMC75F2413A
XTAL1 3 R 33 XTAL2
C2 20p
GND
OUT
Figure 5-5 The crystal circuit connection
Figure 5-7 The external clock from oscillator connection
5.3.2. Phase-lock Loop (PLL)
There is an on-chip PLL circuit available. The PLL takes a reference clock for generating system clock. The on-chip crystal The PLL During clock is used as the reference clock of PLL circuit. output clock rate is four times of reference clock.
5.3.4. Clock Monitoring
A clock monitoring circuit is also available to detect whether the oscillator clock and system clock run normally. If a clock halt is detected, the twelve motor drive PWM pins (TIO3A~F and TIO4A~F) will be set to high-impedance state, regardless their pin function settings, and an interrupt will be issued to notify CPU. Remarkably, the state will be released only by power-on reset if the PWM pins are set to high-impedance state.
power-on or system reset or wake-up from standby, CPU will halt 16384 oscillator reference clocks (FIN) for oscillator and PLL to be stable. The stable time is about 2.7ms when oscillator reference The PLL will output about 1MHz clock when Following diagram shows the clock is 6MHz.
oscillator clock is not available.
relationship between crystal oscillator and PLL circuit.
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External reset Power-on reset Crystal oscillator System clock P_Clk_Ctrl.OSCSF Write P_Clk_Ctrl.OSCSF=1 to clear this flag MCP OSC fail latch OSC fail =1 make MCP3/MCP4 output as Hi-Z Only power-on reset can clear MCP OSC fail latch
Figure 5-8 Clock Fail timing
* P_Clk_Ctrl (0x7007): System Clock Control Register This register is used for monitoring CPU clock status. B15 R/W 0 OSCSF B7 R 0 B14 R/W 0 OSCIE B6 R 0 B5 R 0 B4 R 0 Reserved OSCSF B3 R 0 B13 R 0 B2 R 0 B11 R 0 Reserved Bb2 R 0 b1 R 0 B0 R 0 B10 R 0 b9 R 0 B8 R 0
B15
Oscillator status flag
Read 0: Oscillator operates normally Write 1: Clear this flag
Read 1: Oscillator failed
B14 B10-8
:
OSCIE Reserved
Oscillator fail interrupt enable bit
0: Disable
1: Enable
write "1" to clear this flag
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5.3.5. RC Oscillator
The 200KHz clock that is derived from build-in oscillator is provided for power-on timer and flash controller to generate the necessary control signals meeting the timing specifications of flash erasing and programming. It can be disabled in either sleep mode or standby mode for power saving. Standby mode All modules are disabled in this mode. Power consumption is minimized in this mode. When waking-up, CPU will reset and back to normal operation mode. Other peripherals can be turned off individually by software. Note that if TPM (Timer/PWM Module) channel 3 or channel 4 has been set to PWM output mode, the device will not enter Wait mode or Standby mode. Figure 5-10 shows the Standby mode timing. Table 5-5 the relationship between mode and operation Normal mode When device operates in normal mode, it consumes the maximum power, and all peripherals can be used. CPU PLL Peripherals Wait mode Both of CPU and watchdog are powered-down in wait mode to decrease CPU power consumption. Other peripherals keep their previous states and are operable. When waking up, CPU will resume and execute next instruction. Figure 5-9 shows the Wait mode timing. Table 5-5 shows the relationship between power saving mode and related operation. Wakeup from Wait OFF ON ON Next instruction Standby OFF OFF OFF Reset CPU
5.4. Power Saving Modes
There are three operating modes available in this device: Normal mode, Wait mode, and Standby mode.
Figure 5-9 Wait mode timing
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16384 Slow Clocks Clk200KHz clock System clock Write P_Stdby_Enter=0xA00A to enter Stop mode Stop mode
P_Wakeup_Ctrl .KEYWE
Enable Keychange as wake up source Keychange CPU reset Write 1 to clear this flag
P_Stdby_Enater .B0
Write 1 to clear this flag
P_INT_Status. KEYIF
Figure 5-10 Standby mode timing
5.4.1. Wake-up Sources
The wake-up event may come from the following sources (total 28 sources): Compare Match Timer Timer/PWM Module Channel 0: TPR_0, TGRA_0, TGRB_0, TGRC_0, Position detection change, overflow, underflow Channel 1: TPR_1, TGRA_1, TGRB_1, TGRC_1, Position detection change, overflow, underflow Channel 2: TPR_2, TGRA_2, TGRB_2 Channel 3: TPR_3, TGRD_3 Channel 4: TPR_4, TGRD_4 IO Key change EXINT0 EXINT1 UART SPI Channel 0: CMT_0 compare match Channel 1: CMT_1 compare match
External Interrupt -
Serial Communication Interface -
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* P_Wakeup_Ctrl (0x700F)Wake-up Control Register B15 R/W 0 KEYWE B7 R/W 0 TPM2WE B14 R/W 0 UARTWE B6 R/W 0 PDC1WE B13 R/W 0 SPIWE B5 R/W 0 PDC0WE B12 R/W 0 EXT1WE B4 R/W 0 CMTWE B11 R/W 0 EXT0WE B3 R/W 0 B2 R/W 0 Reserved B10 R/W 0 B9 R/W 0 Reserved B1 R/W 0 B0 R/W 0 B8 R/W 0
B15 B14 B13 B12 B11 B10-8 B7 B6 B5 B4 B3-0
KEYWE UARTWE SPIWE EXT1WE EXT0WE Reserved TPM2WE PDC1WE PDC0WE CMTWE Reserved
Key-change wake-up enable bit UART wake-up enable bit SPI wake-up enable bit External interrupt 1 wake-up enable bit External interrupt 0 wake-up enable bit
0: Disable 0: Disable 0: Disable 0: Disable 0: Disable
1: Enable 1: Enable 1: Enable 1: Enable 1: Enable
TPM channel 2 wake-up enable bit PDC channel 1 wake-up enable bit PDC channel 0 wake-up enable bit Compare match timer wake-up enable bit
0: Disable 0: Disable 0: Disable 0: Disable
1: Enable 1: Enable 1: Enable 1: Enable
* P_Wait_Enter (0x700C)Wait-mode Entrance Registe B15 W 0 B14 W 0 B13 W 0 B12 W 0 WaitCMD B7 W 0 B6 W 0 B5 W 0 B4 W 0 WaitCMD B15-0 WaitCMD Wait-mode Entrance/Status flag 1. 2. 3. 4. Write 0x5005 to enter wait mode (CPU off, PLL on). Write 0x0001 will clear wait flag. Read 0x0001 indicates that it is wake-up from wait mode. Note that to enter Wait mode, MCP channel 3 or 4 must not be set to PWM output mode. In ICE mode, SPMC75F2413A cannot enter into wait mode. B3 W 0 B2 W 0 B1 W 0 B0 R/W 0 B11 W 0 B10 W 0 B9 W 0 B8 W 0
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* P_Stdby_Enter (0x700E)Standby-mode Entrance Register B15 W 0 B14 W 0 B13 W 0 B12 W 0 StdbyCMD B7 W 0 B6 W 0 B5 W 0 B4 W 0 StdbyCMD B15-0 StdbyCMD Standby-mode Entrance/Status flag 1. 2. 3. 4. Write 0xA00A to enter standby mode (CPU off, PLL off). Write 0x0001 will clear standby flag. Read 0x0001 indicates that it is wake-up from Standby mode. Note that to enter Standby mode, MCP channel 3 or 4 must not be set to PWM output mode. In ICE mode, SPMC75F2413A cannot enter into standby mode. B3 W 0 B2 W 0 B1 W 0 B0 R/W 0 B11 W 0 B10 W 0 B9 W 0 B8 W 0
5.5. Interrupt
The SPMC75F2413A has 38 interrupt sources. Interrupt Request) and IRQ0~IRQ7 (Interrupt request). These 38 Besides, interrupt sources can be grouped into two types, FIQ (Fast the SPMC75F2413A also implements a software interrupt, BREAK. The priority of BREAK, FIQ, and IRQ is as follows: BREAK > FIQ > IRQ 0 > IRQ 1 > IRQ 2 > IRQ 3 > IRQ 4 > IRQ 6 > IRQ 7. BREAK and FIQ have higher priority than IRQ. priority. The An IRQ can be If IRQNEST
5.5.1. Interrupt Source
The interrupt may come from the following sources (total 38 sources):
Timer/PWM Module Channel 0: TPR_0, TGRA_0, TGRB_0, TGRC_0, Position detection change, overflow, underflow Channel 1: TPR_1, TGRA_1, TGRB_1, TGRC_1, Position detection change, overflow, underflow Channel 2: TPR_2, TGRA_2, TGRB_2 Channel 3: TPR_3, TGRD_3 Channel 4: TPR_4, TGRD_4 Channel 0: CMT_0 compare match Channel 1: CMT_1 compare match Key change Conversion finished EXINT0 EXINT1 UART SPI FTINT1 FTINT2 Output short Oscillator fail Feb. 16, 2006 Version: 1.1
interrupted by a FIQ, BREAK, or another IRQ that has higher An FIQ can only be interrupted by BREAK. mode is off and more than two IRQ occurred, the priority of IRQ are IRQ0, IRQ1, and IRQ2 ......IRQ7. existed IRQ. However, if a lower priority IRQ occurred first, even a higher priority IRQ cannot interrupt the For example, if IRQ4 is occurred first, IRQ3 is The priority takes over only when two If IRQNEST mode is on, a higher For unable to interrupt IRQ4.
Compare Match Timer IO -
IRQ occurred concurrently.
priority IRQ can interrupt the lower priority IRQ occurred first.
example, if IRQ4 is occurred first, IRQ3 is able to interrupt IRQ4. The current interrupts are listed in Table 5-6. In this table, it shows the interrupt sources, interrupt name, IRQ number and FIQ selection.
A/D Converter -
External Interrupt -
Serial Communication Interface -
Fault Protection -
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Table 5-6 Interrupt sources of each IRQ level IRQ Level Register Check Interrupt Flag P_INT_Status.FTIF P_INT_Status.FTIF P_INT_Status.FTIF IRQ0 (highest) P_INT_Status.FTIF P_INT_Status.OLIF P_INT_Status.OLIF P_INT_Status.OSCSF P_INT_Status.PDC0IF P_INT_Status.PDC0IF P_INT_Status.PDC0IF IRQ1 P_INT_Status.PDC0IF P_INT_Status.PDC0IF P_INT_Status.PDC0IF P_INT_Status.PDC0IF P_INT_Status.PDC1IF P_INT_Status.PDC1IF P_INT_Status.PDC1IF IRQ2 P_INT_Status.PDC1IF P_INT_Status.PDC1IF P_INT_Status.PDC1IF P_INT_Status.PDC0IF P_INT_Status.MCP3IF IRQ3 P_INT_Status.MCP3IF P_INT_Status.MCP4IF P_INT_Status.MCP4IF P_INT_Status.TPM2IF IRQ4 P_INT_Status.TPM2IF P_INT_Status.TPM2IF IRQ5 P_INT_Status.EXT0IF P_INT_Status.EXT1IF P_INT_Status.UARTIF IRQ6 P_INT_Status.UARTIF P_INT_Status.SPIIF P_INT_Status.SPIIF P_INT_Status.KEYIF IRQ7 (Lowest) P_INT_Status.ADCIF P_INT_Status.CMTIF P_INT_Status.CMTIF or P_ADC_Ctrl.ADCIF or P_CMT_Ctrl.CM0IF or P_CMT_Ctrl.CM1IF or P_UART_Status.RXIF or P_UART_Status.TXIF or P_SPI_RxStatus.SPIRXIF or P_SPI_TxStatus.SPITXIF or P_Fault1_Ctrl.FTPINIF or P_Fault2_Ctrl.FTPINIF or P_Fault1_Ctrl.OSF or P_Fault2_Ctrl.OSF or P_OL1_Ctrl.OLIF or P_OL2_Ctrl.OLIF or P_Clk_Ctrl. OSCSF or P_TMR0_Status.TPRIF or P_TMR0_Status.TGAIF or P_TMR0_Status.TGBIF or P_TMR0_Status.TGCIF or P_TMR0_Status.PDCIF or P_TMR0_Status.TCVIF or P_TMR0_Status.TCUIF or P_TMR1_Status.TPRIF or P_TMR1_Status.TGAIF or P_TMR1_Status.TGBIF or P_TMR1_Status.TGCIF or P_TMR1_Status.PDCIF or P_TMR1_Status.TCVIF or P_TMR1_Status.TCUIF or P_TMR3_Status.TPRIF or P_TMR3_Status.TGDIF or P_TMR4_Status.TPRIF or P_TMR4_Status.TGDIF or P_TMR2_Status.TPRIF or P_TMR2_Status.TGAIF or P_TMR2_Status.TGBIF Name FTIN1_INT FTIN2_INT OS1_INT OS2_INT OL1_INT OL2_INT OSCF_INT TPR0_INT TGRA0_INT TGRB0_INT TGRC0_INT PDC0_INT TCV0_INT TUV0_INT TPR1_INT TGRA1_INT TGRB1_INT TGRC1_INT PDC1_INT TCV1_INT TUV1_INT TPR3_INT TGRD3_INT TPR4_INT TGRD4_INT TPR2_INT TGRA2_INT TGRB2_INT EXT0_INT EXT1_INT UART_RX_INT UART_TX_INT SPI_RX_INT SPI_TX_INT IOKEY_INT ADC_INT CMT0_INT CMT1_INT Description Fault input pin 1 interrupt Fault input pin 2 interrupt Output short 1 interrupt Output short 2 interrupt Overload pin 1 interrupt Overload pin 2 interrupt Oscillator failed interrupt Timer 0 TPR interrupt Timer 0 TGRA interrupt Timer 0 TGRB interrupt Timer 0 TGRC interrupt Timer 0 position detection change interrupt Timer 0 counter overflow interrupt Timer 0 counter underflow interrupt Timer 1 TPR interrupt Timer 1 TGRA interrupt Timer 1 TGRB interrupt Timer 1 TGRC interrupt Timer 1 position detection change interrupt Timer 1 counter overflow interrupt Timer 1 counter underflow interrupt Timer 3 TPR interrupt Timer 3 TGRD interrupt Timer 4 TPR interrupt Timer 4 TGRD interrupt Timer 2 TPR interrupt Timer 2 TGRA interrupt Timer 2 TGRB interrupt External 0 interrupt External 1 interrupt UART receive complete interrupt UART transmit ready interrupt SPI receive interrupt SPI transmit interrupt IO Key change interrupt ADC conversion complete interrupt Compare match timer 0 interrupt Compare match timer 1 interrupt
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5.5.2. Interrupt procedure
When the interrupt event occurred, the status is recorded and cleared only by write "1" to clear. If the event occurs and interrupt enable bit has been set, the CPU will entering interrupt request (IRQ) procedure as follows: 1. CPU jumps to interrupt vector to look up the address of corresponding interrupt service routine. 2. Push the data in SR (Status register) and the return address in PC (Program Counter register) to stack memory. 3. CPU jumps to the address of service routine to execute program and clear interrupt flag. 4. Pop the data in SR register to restore the system status. Pop the return address to PC. 5. CPU returns to the original address and keep executing the program.
The timing diagram of interrupt procedure and stack operation is as the following Figure 5-11 and Figure 5-12, respectively.
Figure 5-11 Interrupt procedure timing
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Figure 5-12 Stack memory operation with interrupt procedure
* P_INT_Status (0x70A0): Interrupt Status Register This register is a look-up table for all interrupts status flags. Most clear these flags. Others are the status flags from other registers and read only. B11 R/W 0 EXT0IF B3 R 0 Reserved B10 R 0 ADCIF B2 R 0 OLIF B9 R 0 MCP4IF B1 R 0 OSCSF B8 R 0 MCP3IF B0 R 0 FTIF status flags are composed of some flags. Please refer to Table 5-6 for detail. Only the KEYIF, EXT1IF and EXT0IF can write `1' to B15 R/W 0 KEYIF B7 R 0 TPM2IF B14 R 0 UARTIF B6 R 0 PDC1IF B13 R 0 SPIIF B5 R 0 PDC0IF B12 R/W 0 EXT1IF B4 R 0 CMTIF
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6
KEYIF UARTIF SPIIF EXT1IF EXT0IF ADCIF MCP4IF MCP3IF TPM2IF PDC1IF
Key-change interrupt status flag UART interrupt status flag SPI interrupt status flag External interrupt 1 status flag External interrupt 0 status flag A/D-converter interrupt status flag MCP4 Timer 4 interrupt status flag MCP3 Timer 3 interrupt status flag TPM2 Timer 2 interrupt status flag PDC Timer 1 interrupt status flag 40
0: Not occurred 0: Not occurred 0: Not occurred 0: Not occurred 0: Not occurred 0: Not occurred 0: Not occurred 0: Not occurred 0: Not occurred 0: Not occurred
1: Has occurred 1: Has occurred 1: Has occurred 1: Has occurred 1: Has occurred 1: Has occurred 1: Has occurred 1: Has occurred 1: Has occurred 1: Has occurred Feb. 16, 2006 Version: 1.1
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B5 B4 B3 B2 B1 B0
:
PDC0IF CMTIF Reserved OLIF OSCSF FTIF
PDC Timer 0 interrupt status flag Compare match timer interrupt status flag
0: Not occurred 0: Not occurred
1: Has occurred 1: Has occurred
Overload interrupt status flag Oscillator status flag Fault protection interrupt status flag
0: Not occurred 0: Oscillator normal 0: Not occurred
1: Has occurred 1: Oscillator failed 1: Has occurred
write `1' to clear this flag
* P_INT_Priority (0x70A4): IRQ and FIQ Priority Selection Register This port can set interrupt source as IRQ or FIQ. B15 R/W 0 KEYIP B7 R/W 0 TPM2IP B14 R/W 0 UARTIP B6 R/W 0 PDC1IP B13 R/W 0 SPIIP B5 R/W 0 PDC0IP The default B12 R 0 Reserved B4 R/W 0 CMTIP set as FIQ at P_INT_Priority. B11 R/W 0 EXTIP B3 R 0 Reserved B10 R/W 0 ADCIP B2 R 0 OLIP B9 R/W 0 MCP4IP B1 R/W 0 OSCIP B8 R/W 0 MCP3IP B0 R/W 0 FTIP interrupt source is IRQ. Note: Only one of interrupt source can be
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
KEYIP UARTIP SPIIP Reserved EXTIP ADCIP MCP4IP MCP3IP TPM2IP PDC1IP PDC0IP CMTIP Reserved OLIP OSCIP FTIP
Key-change interrupt priority select bit UART interrupt priority select bit SPI interrupt priority select bit
0: IRQ7 0: IRQ6 0: IRQ6
1: FIQ 1: FIQ 1: FIQ
External interrupt priority select bit ADC interrupt priority select bit MCP Timer 4 interrupt priority select bit MCP Timer 3 interrupt priority select bit TPM Timer 2 interrupt priority select bit PDC Timer 1 interrupt priority select bit PDC Timer 0 interrupt priority select bit CMT interrupt priority select bit
0: IRQ5 0: IRQ7 0: IRQ3 0: IRQ3 0: IRQ4 0: IRQ2 0: IRQ1 0: IRQ7
1: FIQ 1: FIQ 1: FIQ 1: FIQ 1: FIQ 1: FIQ 1: FIQ 1: FIQ
Overload interrupt priority select bit Oscillator fail interrupt priority select bit Fault protection interrupt priority select bit
0: IRQ0 0: IRQ0 0: IRQ0
1: FIQ 1: FIQ 1: FIQ
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* P_MisINT_Ctrl (0x70A8): Miscellaneous Interrupt Control Register This port can be set to enable interrupt. B15 R/W 0 KEYIE B7 R 0 B14 R/W 0 EXT1MS B6 R 0 Write "1" to any bit to enable the interrupt. B13 R/W 0 EXT0MS B5 R 0 B12 R/W 0 EXT1IE B4 R 0 Reserved B11 R/W 0 EXT0IE B3 R 0 B2 R 0 B10 R 0 B9 R 0 Reserved B1 R 0 B0 R 0 B8 R 0
B15 B14 B14 B12 B11 B10-B0
KEYIE EXT1MS EXT0MS EXT1IE EXT0IE Reserved
Key-change interrupt enable bit External interrupt 1 trigger edge select bit External interrupt 0 trigger edge select bit External interrupt 1 enable bit External interrupt 0 enable bit
0: Disable 0: Falling edge trigger 0: Falling edge trigger 0: Disable 0: Disable
1: Enable 1: Rising edge trigger 1: Rising edge trigger 1: Enable 1: Enable
5.6. Reset Management
In SPMC75F2413A, the reset logic is used for leading MCU into a known state when device operates abnormally. The source of reset can be determined by using the reset status bits. The reset circuit can be used for increasing system reliability.
5.6.2. External reset
By pulling external reset pin RESETB to VSS, system reset will be generated and will be released after 16384 crystal clocks.
5.6.1. Power on reset (POR)
A power-on reset is generated when VDD rising is detected. When VDD is rising to acceptable level, the power-up timer starts counting. After finish counting 16384 crystal clock ticks, system reset will be released and CPU starts operating.
Figure 5-13 External reset circuit
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16384 cycles for Power-on Timer 200KHz clock System clock RESET Power-on reset CPU address System reset CPU reset P_Reset_Status .PORF Write P_Reset_Status = 0x5502 to clear this flag P_Reset_Status .EXTRF All GPIO go to Hi-Z state All GPIO Configure GPIO FFF7
16384 cycles for Power-on Timer
FFF7
Write P_Reset_Status = 0x5501 to clear this flag
All GPIO go to Hi-Z state
Figure 5-14 Power-on reset, external reset and power-up timer timing
5.6.3. Low voltage reset (LVR)
When power supply voltage drops below 4.09V, a low voltage reset will be issued. be generated. When LVR is asserted, a system reset will When CPU and all peripherals will be reset.
5.6.5. Illegal address reset (IAR)
The device offers an illegal address reset for preventing system from accessing illegal address. When an illegal address is being accessed, a CPU reset will be generated. Figure 5-17 shows illegal address reset timing.
supply voltage up to 4.19V, device will leave reset status. Figure
5-15 shows the low voltage reset timing.
5.6.6. Illegal instruction reset (IIR)
When an invalid instruction is being decoded by CPU, an illegal instruction reset will be issued and reset CPU. This Figure 5-18 shows the illegal instruction reset timing.
5.6.4. Watchdog timer reset (WDTR)
On-chip watchdog circuitry makes the device entering into reset when the MCU goes into unknown state and without any watchdog clearance. function ensures the MCU does not continue to work in abnormal condition. When "0xA005" is written into P_WatchDog_Clr(W) (0x700B), the watchdog timer will be cleared and continue to count. reset state. Figure 5-16 shows the watchdog timer reset timing. If P_WatchDog_Clr is not written between watchdog overflow intervals, the device will be forced into
Following table shows the effected modules of different reset sources. Table 5-7 Reset source and effected modules Reset Source External Reset Pin Power-on Reset Watchdog Reset Low Voltage Reset CPU V V V V Peripheral V V Option V Feb. 16, 2006 Version: 1.1
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Reset Source Illegal Address Reset Illegal Instruction Reset
CPU V V
Peripheral -
Please refer to P_WatchDog_Ctrl for details
Figure 5-15 Low voltage reset timing
Watchdog reset Watchdog timer
26
27
0
1
2
3
7E
7F
0
1
2
3
7E
7F
0
write P_WatchDog_Clr = $A005 to clear Watchdog Timer P_Reset_Status .WDRF
Figure 5-16 Watchdog timer reset timing
Write P_Reset_Status = $5504 to clear this flag
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CPU address bus
illegal address
FFF7
IAR event System reset CPU reset Write P_Reset_Status = 0x5520 to clear this flag IAR Flag
Figure 5-17 Illegal address reset timing
CPU address bus IIR event System reset CPU reset
FFF7
Write P_Reset_Status = 0x5540 to clear this flag IIR flag
Figure 5-18 Illegal instruction reset timing
* P_Reset_Status(0x7006): Reset Status Register This register shows the flag of reset status for firmware checking. B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 FCHK B7 R 0 Reserved B6 R/W 0 IIRF B5 R/W 0 IARF B4 R 0 Reserved B3 R/W 0 LVRF B2 R/W 0 WDRF B1 R/W 0 PORF B0 R/W 0 EXTRF B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
B15-8 B7 B6 B5 B4 B3 B2
FCHK Reserved IIRF IARF Reserved LVRF WDRF
Flag clear check bits pattern. To properly clear reset flags, these bits must be written to `0x55'. Otherwise, the flags will not be cleared. These bits will be read as `0'.
Illegal instruction reset flag Illegal address reset flag
0: Not occurred 0: Not occurred
1: Occurred 1: Occurred
Low voltage reset flag Watchdog reset flag 45
0: Not occurred 0: Not occurred
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B1 B0
PORF EXTRF
Power-on reset flag External reset pin reset flag
0: Not occurred
1: Occurred
5.7. General Purpose I/O Ports (GPIO)
General purpose I/O ports allow the device to communicate with other devices. To add flexibility and functionality to a device, some parts of I/O pins are multiplexed with an alternative function. These functions can be switched through appropriate registers. For most general I/O ports, the I/O structure contains five parts: data, buffer, direction, attribution, latch and special function enable registers.
P_IOX_Data(W) Keychange Latch Q D EN
Table 5-9 shows the I/O configurations and
P_IOX_Data(R)
P_IOX_Latch
Four programmable I/O ports are available in the device: Port A, Port B, Port C, and Port D. Each I/O pin on these 4 ports can be bit-by-bit configured by software programming. Except Port D, almost every I/O pin on these 4 ports can be programmed as special function. In other words, many special function control signals share with I/O ports.
P_IOX_Attrib(R/W) P_IOX_Buffer(R/W)
Register &
OUT
pu
P_IOX_Dir(R/W)
Control logic
p
Figure 5-19 shows the structure of a typical I/O ports. The
open-drain configuration can be achieved by setting the registers of direction, attribution and buffer as the following table.
Table 5-8 Open-drain Configuration Direction Attribution Buffer Open drain Function 0 1 Table 5-9 I/O Configuration Direction 0 0 0 0 1 1 1 1 Attribution 0 0 1 1 0 0 1 1 Data 0 1 0 1 0 1 0 1 Function Pull Low Pull High Float Float Inverted Inverted Not Inverted Not Inverted Keychange Yes Yes Yes No No No No No Input with pull low Input with pull high Input with float Input with float Output with data inverted (write "0" to the Data Port and will output "1" to the I/O pad) Output with data inverted (write "1" to the Data Port and will output "0" to the I/O pad) Output with buffer (data not inverted) Output with buffer (data not inverted) Description 1 1 0 0 Output high Output low
Default: Input with floating when power on
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P_IOX_Data(R)
Keychange
Latch Q D EN P_IOX_Latch(R)
P_IOX_Data(W)
Register &
OUT
P_IOX_Buffer(R/W)
pull high
Pad
P_IOX_Dir(R/W)
Control logic
P_IOX_Attrib(R/W)
pull low
CL
Figure 5-19 IO structure diagram
All output ports contain a register P_IOx_Buffer (x=A,B,C,D). Therefore, the output data are retained by the register. There are two methods to write data into P_IOx_Buffer. One is P_IOx_Buffer(W), the other is P_IOx_Data(W) (x=A,B,C,D). P_IOx_Data(W) and P_IOx_Buffer(W) have the same result exactly. However, P_IOx_Buffer(R) reads the data stored in P_IOx_Buffer. P_IOx_Data(R) reads the input port: Port A, Port B, PortC and PortD, respectively. As a result, user should pay more attention to the operations on P_IOx_Data. For example, the data in P_IOx_Buffer and data from P_IOx_Data(R) may be different. The P_IOx_Buffer will be altered incorrectly if the bit operations SETB, CLRB and INVB are performed on P_IOx_Data. Therefore, it is suggested that user should perform the bit operations on P_IOx_Buffer (x=A,B,C,D) exclusively. Please refer to Figure 5-20. None of the input ports has a register. Therefore, the input data is desirable to be retained on the input port until it is read in, or read several times and acquire average data before being processed. The input/output timing of Port A is shown as follows.
Large Driving Pins IOA[15:8], IOB[15:12], IOB[5:0], IOC[3:0], and IOC[15:10], total 28 I/O ports support large-current output capability that can direct drive LED.
Key-change Interrupt Pins There are 8 I/O ports, IOA[15:8], support key-change function. Each I/O port can be enable/disable separately. The key-change function is enabled by setting the appropriate direction, attribution and buffer configuration as listed on Table 5-9 and setting P_IOA_KCER to enable the IO port used as key-change source. Next, P_IOA_Latch(R) should be performed to latch the value of Port A. The key-change event occurs if the Port A is different from the value that have stored into P_IOA_Latch. Additionally, the key-change event occurs once until P_IOA_Latch(R) is performed again, which is called one shot. The operation of key-change IOA15 is shown as Figure 5-21.
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IOA[15:0] P_IOA_Dir[15:0] System address bus CPU read strobe 0000
84 ffff P_IOA_Buffer
8004
P_IOA_Data
The input data from IO port is captured at this moment when the CPU reading occurs. System data bus CPU write strobe The time at which data is forwarded to IO port is at the end of write cycle.
Figure 5-20 GPIO input/output timing
84
8004
IOA15/ADCTRG P_IOA_KCER .KC15EN Enable IOA15/ADCTRG as keychange source
P_IOA_Latch.B15 Key change filter delay Read P_IOA_Latch to latch IOA15/ ADCTRG into P_IOA_Latch.B15
Key change One shot one shot make the keychange activated once only P_INT_Status .KEYIF Write P_INT_Status.KEYIF=1 to clear this flag Re-activate keychange by reading P_IOA_Latch again,
Figure 5-21 Keychange timing
* P_IOA_Data (0x7060)IO Port A Data Register Write data into the data register and read data from the I/O pad. Writing data into P_IOA_Data will be the same as writing into P_IOA_Buffer. To prevent unwanted operation at unmodified bit B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 P_IOA_Data (c) Sunplus Innovation Technology Inc. Proprietary & Confidential 48 Feb. 16, 2006 Version: 1.1 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0 data, bit operation instruction should apply at P_IOA_Buffer instead of P_IOA_Data.
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B7 R/W 0
B6 R/W 0
B5 R/W 0
B4 R/W 0 P_IOA_Data
B3 R/W 0
B2 R/W 0
B1 R/W 0
B0 R/W 0
* P_IOA_Buffer (0x7061)IO Port A Buffer Register Reading means to read data from data register. B15 R/W 0 B14 R/W 0 B13 R/W 0 Write data into P_IOA_Buffer will be the same as writing into P_IOA_Data. B12 R/W 0 P_IOA_Buffer B7 R/W 0 Note: B6 R/W 0 B5 R/W 0 B4 R/W 0 P_IOA_Buffer The reading of P_IOA_Data (R)(0x7060) and P_IOA_Buffer (R)(0x7061) is through different physical path. The data is from I/O pad by reading P_IOA_Data (R)(0x7060). The data is form I/O buffer by reading P_IOA_Buffer (R)(0x7061). B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
* P_IOA_Dir (0x7062)IO Port A Direction Register Read/Write direction vector from/into the Direction Register. B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 P_IOA_Dir B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 P_IOA_Dir * P_IOA_Attrib (0x7063)IO Port A Attribute Register Read/Write attribute vector from/into the Attribute Register. B15 R/W 1 B14 R/W 1 B13 R/W 1 B12 R/W 1 P_IOA_Attrib B7 R/W 1 B6 R/W 1 B5 R/W 1 B4 R/W 1 P_IOA_Attrib * P_IOA_Latch (0x7064)IO Port A Latch Register Read this port to latch data on the I/O PortA for key change wakeup before getting into sleep mode. B15 R 0 B14 R 0 B13 R 0 B12 R 0 P_IOA_Latch B11 R 0 B10 R 0 B9 R 0 B8 R 0 B3 R/W 1 B2 R/W 1 B1 R/W 1 B0 R/W 1 B11 R/W 1 B10 R/W 1 B9 R/W 1 B8 R/W 1 B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
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B7 R 0
B6 R 0
B5 R 0
B4 R 0 Reserved
B3 R 0
B2 R 0
B1 R 0
B0 R 0
* P_IOA_SPE (0x7080)IO Port A Special Function Enable Register B15 R 0 Reserved B7 R 0 B14 R/W 0 TCLKDEN B6 R 0 B13 R/W 0 TCLKCEN B5 R 0 B12 R/W 0 TCLKBEN B4 R 0 Reserved B11 R/W 0 TCLKAEN B3 R 0 B10 R/W 0 TIO2BEN B2 R 0 B9 R/W 0 TIO2AEN B1 R 0 B8 R 0 Reserved B0 R 0
B15 B14 B13 B12 B11 B10 B9 B8-0
Reserved TCLKDEN TCLKCEN TCLKBEN TCLKAEN TIO2BEN TIO2AEN Reserved External clock D input pin External clock C input pin External clock B input pin External clock A input pin P_TMR2_TGRB input capture input/PWM output enable P_TMR2_TGRA input capture input/PWM output enable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable
* P_IOA_KCER (0x7084)IO Port A Key Change Enable Register B15 R/W 0 KC15EN B7 R 0 B14 R/W 0 KC14EN B6 R 0 B13 R/W 0 KC13EN B5 R 0 B12 R/W 0 KC12EN B4 R 0 Reserved B11 R/W 0 KC11EN B3 R 0 B10 R/W 0 KC10EN B2 R 0 B9 R/W 0 KC9EN B1 R 0 B8 R/W 0 KC8WE B0 R 0
B15 B14 B13 B12 B11 B10 B9 B8 B7-0
KC15EN KC14EN KC13EN KC12EN KC11EN KC10EN KC9EN KC8EN Reserved
PortA.15 Key change enable PortA.14 Key change enable PortA.13 Key change enable PortA.12 Key change enable PortA.11 Key change enable PortA.10 Key change enable PortA.9 Key change enable PortA.8 Key change enable
0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable
1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable
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* P_IOB_Data (0x7068)IO Port B Data Register Write data into data register and read from I/O pad. B15 R/W 0 B14 R/W 0 B13 R/W 0 Writing data B12 R/W 0 P_IOB_Data B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 P_IOB_Data * P_IOB_Buffer (0x7069)IO Port B Buffer Register Write data into the data register and read data from the I/O buffer. Writing data into P_IOB_Buffer will be the same as writing into B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 P_IOB_Buffer B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0 P_IOB_Data. B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 prevent unwanted operation at unmodified bit data, bit operation instruction should apply at P_IOB_Buffer instead of P_IOB_Data. B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
into P_IOB_Data will be the same as writing into P_IOB_Buffer. To
B7 R/W 0
B6 R/W 0
B5 R/W 0
B4 R/W 0 P_IOB_Buffer
B3 R/W 0
B2 R/W 0
B1 R/W 0
B0 R/W 0
reading
Note: The reading of P_IOB_Data (R)(0x7068) and P_IOB_Buffer (R)(0x7069) is through different physical path. The data is from I/O pad by P_IOB_Data (R)(0x7068). The data is form I/O buffer by reading P_IOB_Buffer (R)(0x7069).
* P_IOB_Dir (0x706A)IO Port B Direction Register Read/Write direction vector from/into the Direction Register. B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 P_IOB_Dir B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 P_IOB_Dir * P_IOB_Attrib (0x706B)IO Port B Attribute Register Read/Write attribute vector from/into the Attribute Register. B15 R/W 1 B14 R/W 1 B13 R/W 1 B12 R/W 1 P_IOB_Attrib B11 R/W 1 B10 R/W 1 B9 R/W 1 B8 R/W 1 B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
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B7 R/W 1
B6 R/W 1
B5 R/W 1
B4 R/W 1 P_IOB_Attrib
B3 R/W 1
B2 R/W 1
B1 R/W 1
B0 R/W 1
* P_IOB_SPE (0x7081)IO Port B Special Function Enable Register B15 R 0 B14 R 0 B13 R 0 Reserved B7 R/W 0 OL1EN B6 R/W 0 FTIN1EN B5 R/W 1 U1EN B4 R/W 1 V1EN B3 R/W 1 W1EN B12 R 0 B11 R 0 B10 R/W 0 TIO0AEN B2 R/W 1 U1NEN B9 R/W 0 TIO0BEN B1 R/W 1 V1NEN B8 R/W 0 TIO0CEN B0 R/W 1 W1NEN
B15-11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Reserved TIO0AEN TIO0BEN TIO0CEN OL1EN FTIN1EN U1EN V1EN W1EN U1NEN V1NEN W1NEN P_TMR0_TGRA input capture input/PWM output pin or 0: Disable position detection input enable P_TMR0_TGRB input capture input/PWM output pin or 0: Disable position detection input enable P_TMR0_TGRC input capture input/PWM output pin or 0: Disable position detection input enable Overload protection input 1 enable External fault protection input 1 enable U1 pin mode selection V1 pin mode selection W1 pin mode selection U1N pin mode selection V1N pin mode selection W1N pin mode selection 0: Disable 0: Disable 0: GPIO 0: GPIO 0: GPIO 0: GPIO 0: GPIO 0: GPIO 1: Enable 1: Enable 1: U1 phase 1: V1 phase 1: W1 phase 1: U1N phase 1: V1N phase 1: W1N phase 1: Enable 1: Enable 1: Enable
* P_IOC_Data (0x7070)IO Port C Data Register Write data into data register and read from I/O pad. Writing data operation instruction should apply at P_IOC_Buffer instead of P_IOC_Data. B11 R/W 0 P_IOC_Data B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 P_IOC_Data B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
into P_IOC_Data will be the same as writing into P_IOC_Buffer. To prevent unwanted operation at unmodified bit data, bit B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0
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* P_IOC_Buffer (0x7071)IO Port C Buffer Register Write data into the data register and read data from the I/O buffer. Writing data into P_IOC_Buffer will be the same as writing into B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 P_IOC_Buffer B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 P_IOC_Buffer Note: The reading of P_IOC_Data (R)(0x7070) and P_IOC_Buffer (R)(0x7071) is through different physical path. The data is from I/O pad by reading P_IOC_Data (R)(0x7070). The data is form I/O buffer by reading P_IOB_Buffer (R)(0x7071) * P_IOC_Dir (0x7072)IO Port C Direction Register Read/Write direction vector from/into the direction register. B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 P_IOC_Dir B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 P_IOC_Dir * P_IOC_Attrib (0x7073)IO Port C Attribute Register Read/Write attribute vector from/into the Attribute Register. B15 R/W 1 B14 R/W 1 B13 R/W 1 B12 R/W 1 P_IOC_Attrib B7 R/W 1 B6 R/W 1 B5 R/W 1 B4 R/W 1 P_IOC_Attrib * P_IOC_SPE (0x7082)IO Port C Special Function Enable Register B15 R/W 1 W2NEN B7 R/W 0 TIO1CEN B14 R/W 1 V2NEN B6 R/W 0 TIO1BEN B13 R/W 1 U2NEN B5 R/W 0 TIO1AEN B12 R/W 1 W2EN B4 R/W 0 Reserved B11 R/W 1 V2EN B3 R/W 0 EXINT1EN B10 R/W 1 U2EN B2 R/W 0 EXINT0EN B9 R/W 0 FTIN2EN B1 R/W 0 Reserved B8 R/W 0 OL2EN B0 R/W 0 B3 R/W 1 B2 R/W 1 B1 R/W 1 B0 R/W 1 B11 R/W 1 B10 R/W 1 B9 R/W 1 B8 R/W 1 B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0 B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0 P_IOC_Data.
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B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1-0
W2NEN V2NEN U2NEN W2EN V2EN U2EN FTIN2EN OL2EN TIO1CEN TIO1BEN TIO1AEN Reserved EXINT1EN EXINT0EN Reserved
W2N pin mode selection V2N pin mode selection U2N pin mode selection W2 pin mode selection V2 pin mode selection U2 pin mode selection External fault protection input 2 enable Overload protection input 2 enable P_TMR1_TGRC input capture input/PWM output pin or position detection input enable P_TMR1_TGRB input capture input/PWM output pin or position detection input enable P_TMR1_TGRA input capture input/PWM output pin or position detection input enable External interrupt input 1 enable External interrupt input 0 enable
0: GPIO 0: GPIO 0: GPIO 0: GPIO 0: GPIO 0: GPIO 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable
1: W2N phase 1: V2N phase 1: U2N phase 1: W2 phase 1: V2 phase 1: U2 phase 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable
0: Disable 0: Disable
1: Enable 1: Enable
* P_IOD_Data (0x7078)IO Port D Data Register Write data into data register and read from I/O pad. Write data operation instruction should apply at P_IOD_Buffer instead of P_IOD_Data. B11 R/W 0 P_IOD_Data B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 P_IOD_Data * P_IOD_Buffer (0x7079)IO Port D Buffer Register Write data into the data register and read data from the I/O buffer. Writing data into P_IOD_Buffer will be the same as writing into B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 P_IOD_Buffer B7 R/W 0 Note: B6 R/W 0 B5 R/W 0 B4 R/W 0 P_IOD_Buffer The reading of P_IOD_Data (R)(0x7078) and P_IOD_Buffer (R)(0x7079) is through different physical path. The data is from I/O pad by reading P_IOD_Data (R)(0x7078). The data is form I/O buffer by reading P_IOD_Buffer (R)(0x7079). B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0 P_IOD_Data. B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
into P_IOD_Data will be the same as writing into P_IOD_Buffer. To prevent unwanted operation at unmodified bit data, bit B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0
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* P_IOD_Dir (0x707A)IO Port D Direction Register Read/Write direction vector from/into the direction register. B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 P_IOD_Dir B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 P_IOD_Dir * P_IOD_Attrib (0x707B)IO Port D Attribute Register Read/Write attribute vector from/into the Attribute Register. B15 R/W 1 B14 R/W 1 B13 R/W 1 B12 R/W 1 P_IOD_Attrib B7 R/W 1 B6 R/W 1 B5 R/W 1 B4 R/W 1 P_IOD_Attrib B3 R/W 1 B2 R/W 1 B1 R/W 1 B0 R/W 1 B11 R/W 1 B10 R/W 1 B9 R/W 1 B8 R/W 1 B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
5.8. Timer/PWM Module (TPM)
There are five TPM timer channels (PDC0, PDC1, TPM2, MCP3, and MCP4) on the SPMC75F2413A chip. MCP3 and MCP4 timer channels provide two sets of full function for three-phase, six independent PWM output capabilities. PDC0 and PDDC1 timer channels include the three programmable special function pins for input capture, output compare, PWM output, and position detection circuits. TPM2 is a general-purpose timer with input All of these capture, compare output and PWM output capability. sources. Features are listed below. MCP3 and 4 contains PWM or logic level waveform outputs, dead-time generation, fault protection, and overload protection function Interrupt logics for PDC0, PDC1, TPM2, MCP3 and MCP4.
5.9. PDC TIMER 0 AND 1 5.9.1. Module Introduction
SPMC75F2413A provides two channels of 16 bit PDC (Phase Detection Control, PDC) timers used for capture function and PWM operation. In addition, supports position detection features for Brushless-DC motor application. The PDC timers are very useful for mechanical speed calculation including ACI and BLDC motor. For BLDC motor, its commutation for change current conduction is according to position information. Figure 5-22 shows the block diagram of entire PDC timers, channel 0 and channel 1. For details of PDC timer specification, please refer to Table 5-10.
TPM timers provide independent time base at different input clock Maximum 20 programmable PWM output pins (channel 0-4) / 8 input capture pins (channel 0-2) Maximum two set of 6-phase PWM output is possible to drive two AC induction or brush-less DC motors simultaneously (channel 3 and 4) Eight counter input clock selection for each channel A/D converter conversion start trigger can be generated PDC0 and 1 each supports 3-channel input capture, compare output, and PWM output function PDC0 and 1 each supports phase counting mode for quadrature phase encoder inputs PDC0 and 1 also support position detection function for motor control applications TPM2 supports 2-channel input capture, compare output, and PWM output function (c) Sunplus Innovation Technology Inc. Proprietary & Confidential 55
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FCK Internal Clock
Up_Down Enable TBR TCNT Clear
16 Bits Counter
Down_phase
TCLKA_DEG
TCLKB_DEG
Counter Control and Timer General Register Control
Input Edge
Up_phase
Compare Match And PWM Logic
Input Capture Logic
Position
External Clock
Position Detection Logic
TCLKA
TCLKB
Timer Output
Timer input Position
Timer input
Figure 5-22 PDC timers block diagram
Table 5-10 PDC timers specification Function Clock sources Internal clock: External clock: IO pins TIO0A TIO0B TIO0C Timer general register P_TMR0_TGRA P_TMR0_TGRB P_TMR0_TGRC Timer buffer register P_TMR0_TBRA P_TMR0_TBRB P_TMR0_TBRC Timer register Capture sample clock Counting edge period and counter P_TMR0_TPR P_TMR0_TCNT Internal clock: FCK/1, FCK/2, FCK/4, FCK/8 Rising Falling Both edge Counter clear source Cleared on TIO0A, TIO0B, and TIO0C capture input. Cleared on P_POS0_DectData position detection data changes. Cleared on P_TMR0_TPR compare matches. Input capture function Yes 56 Cleared on TIO1A, TIO0B, and TIO0C capture input. Cleared on P_POS1_DectData position detection data changes. Cleared on P_TMR1_TPR compare matches. Yes Feb. 16, 2006 Version: 1.1 PDC Timer 0 PDC Timer 1
FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024 TCLKA, TCLKB TIO1A TIO1B TIO1C P_TMR1_TGRA P_TMR1_TGRB P_TMR1_TGRC P_TMR1_TBRA P_TMR1_TBRB P_TMR1_TBRC P_TMR1_TPR P_TMR1_TCNT
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Function PWM compare 1 output match function output 0 output Output Hold Yes Yes Yes Yes Yes
PDC Timer 0 Yes Yes Yes Yes Yes
PDC Timer 1
Edge-aligned PWM Center-aligned PWM Phase counting mode Timer buffer operation AD convert start trigger Interrupt sources
Yes, phase inputs are TCLKA/TCLKB Yes P_TMR0_TGRA compare match Timer 0 TPR interrupt Timer 0 TGRA interrupt Timer 0 TGRB interrupt Timer 0 TGRC interrupt Timer 0 PDC interrupt Timer 0 overflow interrupt Timer 0 underflow interrupt
Yes, phase inputs are TCLKC/TCLKD Yes P_TMR1_TGRA compare match Timer 1 TPR interrupt Timer 1 TGRA interrupt Timer 1 TGRB interrupt Timer 1 TGRC interrupt Timer 1 PDC interrupt Timer 1 overflow interrupt Timer 1 underflow interrupt
5.9.2. PDC Timer Counting Operation
Each on-chip PDC timer has the following five possible counting operations Timer mode operation. Directional phase counting mode 1 to 4. Count on external clock input pin TCLKA or TCLKB. Edge-aligned PWM mode (continuous up counting, PWM output mode). Center-aligned PWM mode (continuous up/down counting, PWM output mode). The overflow flag is set when the value of timer counter register reaches 0xFFFF and TCVIF flag is set. The overflow interrupt request is generated when TCVIE bit is set in P_TMRx_INT (x = 0, 1) register. The compare match event of general register occurs when timer counter register matches the content of TGRA, TGRB or TGRC register. It generates the general register compare match interrupt when TGAIE, TGBIE or TGCIE bit is set in the corresponding timer interrupt enable register. The initial value of P_TMRx_TPR (x = 0, 1) can be any value from 0x0000 to 0xFFFF. Either the external clock input pin or internal The PDC timer continuous up counting according to the input clock sources from the configuration of TMRPS that is defined in corresponding timer control register. The timer counter register will be cleared to zero when the register value matches that of the timer period register and period compare match event interrupt flag TPRIF is set. The period interrupt request is generated when clock source FCK can be selected as the clock source of the timer. The continuous up counting mode is extremely suitable for the generation of edge-triggered or asynchronous PWM waveforms and sampling periods in digital motor control systems.
Figure 5-23
PPRIE bit is set in P_TMRx_INT (x = 0, 1) register. Once the timer counter register became as 0x0000, the underflow event flag TCUIF is set. The underflow interrupt request is generated when TCUIE bit is set in P_TMRx_INT (x = 0, 1) register.
5.9.2.1. Continuous Up Counting Mode with Edge-Aligned PWM
Each timer channel can be configured as edge-aligned PWM mode by setting MODE bits in P_TMRx_Ctrl (x = 0, 1). At this mode, the counter acts as up-counting timer and counts from 0x0000 to the value of timer period register. User must configure P_TMRx_TPR (x = 0 ~ 1) register, set counter clear source (CCLS) as cleared by timer period compare match and enable Port B/C specific function for compare match output pin.
shows the normal continuous up counting mode of the PDC timer.
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P_TMRx_TPR = 8 8 7 P_TMRx_TPR = 5 5 4 3 2 1 P_TMRx_TCNT 0 0 1 0 2 1 3 2 4 3 P_TMRx_TPR = 5 5 4 5 6
Counter clock source
Figure 5-23 Continuous up counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b)
At edge-aligned PWM mode, user must set P_TMRx_TPR (x= 0, 1) period register and P_TMRx_TGRy (y = A, B, C) general register then set counter clear source (CCLS) as cleared by timer period
compare match. The output condition of compare match can be configured by P_TMRx_IOCtrl (x= 0, 1) register.
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Figure 5-25 Figure 5-24 shows the normal continuous up counting mode for edge-aligned PWM generation of timer 0.
The PDC timer module has two channels and can perform PWM compare match output function up to six pins output. The output waveforms have active low at compare match, active high at compare match and output hold for the corresponding TIOxA, TIOxB, TIOxC (x = 0, 1) output pin using compare match with P_TMRx_TGRA, P_TMRx_TGRB, P_TMRx_TGRC (x = 0, 1)
register respectively. Figure 5-26 shows the programming flowchart of PWM compare match output operation. Figure 5-27 is an example of edge aligned PWM. The correlations between the configuration of P_TMR0_IOCtrl and PWM output, the register TGRx and interrupt status flag TGxIF(x=A, B, C) are shown, respectively.
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Figure 5-25 Edge-Aligned mode PWM
Compare match output operation
Descriptions: [1.] Setup the TGRA/TGRB/TGRC value to generate the desired waveform width.
Setup TGR register value
[1]
[2.]
Setup the CCLS bits to 111'b so that period register determines the period and counter clear source,
Setup period and counter clear source
[3.]
Set the bits TIO0AEN, TIO0BEN, TIO0CEN to 1 in the P_IOB_SPE register and configures the corresponding IO pin to output mode.
[2]
Enable timer special function
[4.]
Select
compare
match
output
mode
through
[3]
[5.]
P_TMRx_IOCtrl (x = 0, 1) register. Start the counting operation with the bit TMR0ST or TMR1ST is set in P_TMR_Start register.
Select waveform output type
[4]
Start counter
[5]
Figure 5-26 Example programming flowchart of PWM compare match output operation
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P_TMR0_TGRA[15:0] P_TMR0_TGRB[15:0] P_TMR0_TGRC[15:0] P_TMR0_TPR[15:0] P_TMR0_TCNT[15:0] P_TMR0_Status .TCDF P_TMR0_Status .TPRIF P_TMR0_Status .TGAIF 0
2 7 A F 123456789ABCDEF0123456789ABCDEF01
Write TMR0_Status.TGAIF=1 to clear this flag
P_TMR0_Status .TGBIF P_TMR0_Status .TGCIF
P_IOB_SPE[15:0]
700 Write P_IOB_Dir to configure IOs of special function as output
P_IOB_Dir[15:0] P_TMR0_IOCtrl[15:0]
700 212
IOB10/TIO0A IOB9/TIO0B IOB8/TIO0C
P_TMR0_IOCtrl = 212: 1. IOA as initial 1 output, 0 output at compare match 2. IOB as initial 0 output, 1 output at compare match 3. IOC as initial 1 output, 0 output at compare match
Figure 5-27 TMR0 edge aligned PWM
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5.9.2.2. Timer mode Operation
The Timer mode can be selected by setting MODE in P_TMRx_Ctrl (x=0, 1). Except output waveform, it operates the same as continuous up counting mode with edge-aligned PWM. The first compare match event of general register occurs when timer counter register matches the content of TGRA, TGRB or TGRC register and the output will transits in the way set by IOAMODE, IOBMODE and IOCMODE, respectively. If compare match event occurs again, the compare match interrupt flag will be set but output waveform retain. Figure 5-28 shows the output timing in Timer mode.
Figure 5-28 Timer mode output timing
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5.9.2.3. Continuous up/down counting mode with Center-Aligned PWM
The operation of continuous up/down counting mode is the same as up counting mode except the timer period register defines the middle transition point of complete counting process. The counting direction changes from up to down when the timer counter register reaches the timer period register. The period of the timer is two times of P_TMRx_TPR (x = 0, 1) of the scaled clock input and the setting of CKEGS in the P_TMRx_Ctrl (x = 0, 1) register. Figure
5-29 shows the continuous up/down counting mode operation.
to zero. The period, underflow, overflow interrupts behaves the same manner as described in the continuous up counting mode. The counting direction is recorded at TCDF bit in the P_TMRx_Status (x = 0, 1) register. Either the external clock input pin or internal clock source FCK can be selected as the clock source of the timer. Figure 5-30 shows the center-aligned mode PWM at continuous up/down counting mode of timer 0. Figure 5-31 is an example of center aligned PWM. The
The initial value of the timer period register can be any value from 0x0000 to 0xFFFF. When the value of the timer counter register equals to timer period register, the PDC timer start to count down
correlations between the configuration of P_TMR0_IOCtrl and PWM output, the register TGRx and interrupt status flag TGxIF(x=A, B, C) are shown, respectively.
P_TMRx_TPR = 5 5 4 3 2 1 P_TMRx_TCNT 0 4 3 2 1 0 1 2 P_TMRx_TPR = 3 3 2 1 0 1 2 P_TMRx_TPR = 3 3 2 1
Counter clock source
Figure 5-29 Continuous up/down counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b)
P_TMR0_TPR = 5 5 4 3 2 1 P_TMR0_TCNT 0 4 3 2 1 0 1 2 P_TMR0_TPR = 3 3 2 1 0 1 2 P_TMR0_TPR = 3 3 2 1
Counter clock source Active High P_TMR0_IOCtrl.IOAMODE = 0x01
TIO0A pin
Figure 5-30 Center-aligned mode PWM
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P_TMR0_TGRA[15:0] P_TMR0_TGRB[15:0] P_TMR0_TGRC[15:0] P_TMR0_TPR[15:0] P_TMR0_TCNT[15:0] P_TMR0_Status .TCDF P_TMR0_Status .TPRIF P_TMR0_Status .TGAIF 0
2 7 A F 123456789ABCDEFEDCBA9876543210123
Write TMR0_Status.TGAIF=1 to clear this flag
P_TMR0_Status .TGBIF P_TMR0_Status .TGCIF
P_IOB_SPE[15:0]
700 Write P_IOB_Dir to configure IOs of special function as output
P_IOB_Dir[15:0] P_TMR0_IOCtrl[15:0]
700 121
IOB10/TIO0A IOB9/TIO0B IOB8/TIO0C
P_TMR0_IOCtrl = 121: 1. IOA as initial 0 output, 1 output at compare match 2. IOB as initial 1 output, 0 output at compare match 3. IOC as initial 0 output, 1 output at compare match
Figure 5-31 TMR0 center aligned PWM
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5.9.2.4.
Input Capture Operation
The powerful and flexible input capture function provides the essential feature for the motor control. Table 5-11 shows the input capture configurations settings and results. When the input capture function is selected, the pulse width or period on input pin can be measured. Figure 5-33 shows the programming flowchart of input capture operation. Figure 5-34 is an example of input capture TIO0x (x=A, B, C). The correlations between the configuration of P_TMR0_IOCtrl and interrupt even are shown.
The capture function activation and the input edge at which the interrupt status flag issued are determined by the bits of IOAMOD, IOBMODE and IOCMODE in the P_TMRx_IOCtrl (x = 0, 1) register, respectively. It can be the rising edge, falling edge or both edge. The value of counter is always transferred to TGRx (x=A, B, C) and TBRx (x=A, B, C) at the rising and falling edge of corresponding input capture port, respectively. The counter register, P_ TMRx_TCNT (x = 0, 1) can be cleared according to the setting of CCLS in P_TMRx_Ctrl (x = 0, 1) register. The counter clear source can be one of TIO0A, TIO0B and TIO0C at the selected edge according to CLEGS in P_TMRx_Ctrl (x = 0, 1).
Figure 5-32 input capture signal connected to TIO0A
Table 5-11 Input capture configuration settings and results Input capture settings CLEGS CCLS IOAMOD P_TMR0_TGRA = period (40 ms) P_TMR0_TBRA = T1 (25ms) P_TMR0_TGRA = period (40 ms) P_TMR0_TBRA = T1 (25ms) P_TMR0_TGRA = period (40 ms) P_TMR0_TBRA = T1 (25ms) P_TMR0_TGRA = T2 (15 ms) P_TMR0_TBRA = period (40ms) P_TMR0_TGRA = T2 (15 ms) P_TMR0_TBRA = period (40ms) P_TMR0_TGRA = T2 (15 ms) P_TMR0_TBRA = period (40ms) P_TMR0_TGRA = T2 (15 ms) P_TMR0_TBRA = T1 (25ms) P_TMR0_TGRA = T2 (15 ms) P_TMR0_TBRA = T1 (25ms) P_TMR0_TGRA = T2 (15 ms) P_TMR0_TBRA = T1 (25ms) Description Results
Rising edge TIO0A Rising edge Counter cleared at rising edge, interrupt at rising edge Rising edge TIO0A Falling edge Counter cleared at rising edge, interrupt at falling edge Rising edge TIO0A Both edge Counter cleared at rising edge, interrupt at both edge
Falling edge TIO0A Rising edge Counter cleared at falling edge, interrupt at rising edge Falling edge TIO0A Falling edge Counter cleared at falling edge, interrupt at falling edge Falling edge TIO0A Both edge Both edge Both edge Both edge Counter cleared at falling edge, interrupt at both edge
TIO0A Rising edge Counter cleared at both edge, interrupt at rising edge TIO0A Falling edge Counter cleared at both edge, interrupt at falling edge TIO0A Both edge Counter cleared at both edge, interrupt at both edge
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Input capture operation
Descriptions: [1.] Select TIOxA, TIOxB, or TIOxC (x=0, 1) as counter clear source, write value to CCLS bits in P_TMRx_Ctrl (x = 0, 1) register.
Select TGR as counter clear source
[1]
[2.] [3.] Setup the counter clear edge by configuring CLEGS: Select capture input interrupt edge as rising, falling, or both edge with setting of bits IOxMOD (x = A, B, C). [4.] Enable capture interrupt in P_TMRx_INT (x = 0, 1) register if necessary.
Setup counter clear edge
[2]
Select capture detection edge
[3]
[5.] Start the counting operation with the bit TMR0ST or TMR1ST is set in P_TMR_Start register.
Enable capture interrupt
[4]
Start counter
[5]
Figure 5-33 Example programming flowchart of input capture operation
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Figure 5-34 Capture input signal width and cycle
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5.9.2.5. Timer 0 and 1 Control Registers
The P_TMRx_Ctrl (x = 0, 1) configures the selection of timer clock source, counter clock edge, counter clear source, counter clear edge, capture input sample clock and timer operating modes. TCLKA, TCLKB clock input will be sampled by system clock FCK. Any pulse narrower than four sampling clocks will be ignored. * P_TMR0_Ctrl (0x7400): Timer 0 Control Register * P_TMR1_Ctrl (0x7401): Timer 1 Control Register B15 R/W 0 SPCK B7 R/W 0 B6 R/W 0 CCLS B15-B14 SPCK Capture input sample 00: FCK/1 clock select B13-B10 MODE Modes select 10: FCK/4 0000: Timer mode 0101: Phase counting mode 2 0111: Phase counting mode 4 1x1x: Center-aligned PWM mode B9-B8 CLEGS Counter clear edge in 00: do not clear input capture mode B7-B5 CCLS Counter clear source select input (x = 0, 1) change 6 times 10: falling edge 000: TCNT clearing disabled 01: rising edge 11: both edge 001: TCNT cleared by TIOxA (x = 0, 1) capture input 010: TCNT cleared by TIOxB (x = 0, 1) capture 011: TCNT cleared by TIOxC (x = 0, 1) capture input TCNT cleared by every P_POSx_DectData (x = 0, 1) change 3 times 110: TCNT cleared by P_POSx_DectData (x = 111: TCNT cleared by P_TMRx_TPR (x = 0, 0, 1) position detection data change B4-B3 CKEGS Clock edge select 00: Count at rising edge 1X: Count at both edges B2-B0 TMRPS Timer pre-scalar select 00: Counts on FCK /1 010: Counts on FCK /16 100: Counts on FCK /256 110: Counts on TCLKA pin input 001: Counts on FCK /4 011: Counts on FCK /64 101: Counts on FCK /1024 111: Counts on TCLKB pin input 1) compare match 01: Count at falling edge 100: TCNT cleared by every P_POSx_DectData 101: B5 R/W 0 B4 R/W 0 CKEGS 01: FCK/2 11: FCK/8 0100: Phase counting mode 1 0110: Phase counting mode 3 1x0x: Edge-aligned PWM mode B14 R/W 0 B13 R/W 0 B12 R/W 0 MODE B3 R/W 0 B2 R/W 0 B1 R/W 0 TMRPS B11 R/W 0 B10 R/W 0 B9 R/W 0 CLEGS B0 R/W 0 B8 R/W 0 When programmed at counting on both edge, the input clock is halved. When MODE bits are set to phase counting mode, the counting phase input is TCLKA/TCLKB on timer 0 and TCLKC/TCLKD on timer 1. The time clock source should be assigned to internal clock in phase counting mode.
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5.9.2.6.
Timer 0 and 1 Period Register
up-/down-counting mode) according to MODE bits programmed in P_TMRx_Ctrl (x = 0, 1) registers. Its default value is 0xFFFF. When P_TMRx_TPR (x = 0, 1) register is set to 0x0000, the P_TMRx_TCNT (x = 0, 1) register counter will stop counting and remain at 0x0000. When
The P_TMRx_TPR (x = 0, 1) is a 16-bit readable/writable register. It is used to set the period of PWM waveform. P_TMRx_TCNT (x = 0, 1) register reaches P_TMRx_TPR (x = 0, 1) register value, P_TMRx_TCNT (x = 0, 1) register will be cleared to 0x0000 (up-counting mode) or start down-count (continuous * P_TMR0_TPR (0x7435): Timer 0 Period Register * P_TMR1_TPR (0x7436): Timer 1 Period Register B15 R/W 1 B14 R/W 1 B13 R/W 1 B12 R/W 1
B11 R/W 1 TMRPRD
B10 R/W 1
B9 R/W 1
B8 R/W 1
B7 R/W 1
B6 R/W 1
B5 R/W 1
B4 R/W 1 TMRPRD
B3 R/W 1
B2 R/W 1
B1 R/W 1
B0 R/W 1
5.9.2.7. Timer 0 and 1 General and Buffer Register
TGRA, TGRB, TGRC are 16-bit registers. PDC Timer has six timer general registers, three for each channel. The TGR registers are dual function 16-bit readable/writable registers, functioning as either PWM output or input capture registers. The values in TGR and TCNT are constantly compared with each other when the TGR registers are used as PWM output registers. When the both values match, the TGAIF, TGBIF, TGCIF bits in corresponding timer interrupt status register are set to 1. Compare match outputs can be selected by TIOxA, TIOxB and TIOxC (x = 0, 1). When the TGR registers are used as input capture registers, the TCNT value is stored at the rising edge of input capture port. When PWM mode, edge-aligned PWM mode, or center-aligned PWM mode is selected, the TGR register behaves as the duty ratio value register. Upon reset, the TGR registers are initialized to 0x0000. The timer buffer registers TBRA, TBRB and TBRC are the double buffers of TGRA, TGRB and TGRC, respectively. The value of TGRx (x=A, B, C) can automatically be updated when the period compare match event occurs. That is, the duty ratio value will not be updated until one period ends completely. When the TBR registers are used as input capture registers, the TCNT value is stored at the falling edge of input capture port. When bits CCLS are set to 100'b, 101'b, 110'b, the PDC timer behaves as PDC mode used for BLDC motor application. The hall position signals are connected to TIOxA, TIOxB, TIOxC (x = 0, 1). The TCNT register is stored to TGRA register according to bits value of CCLS and CLEG bits should be assigned to clear on both edge. When position detection change event occurred, the TCNT register will be latched to TGRA then reset to 0x0000. User could use this information to read the correct TGRA value to calculate the motor speed.
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* P_TMR0_TGRA (0x7440): Timer 0 General Register A * P_TMR0_TGRB (0x7441): Timer 0 General Register B * P_TMR0_TGRC (0x7442): Timer 0 General Register C * P_TMR1_TGRA (0x7443): Timer 1 General Register A * P_TMR1_TGRB (0x7444): Timer 1 General Register B * P_TMR1_TGRC (0x7445): Timer 1 General Register C B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 TMRGLR B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 TMRGLR * P_TMR0_TBRA (0x7450): Timer 0 Buffer Register A * P_TMR0_TBRB (0x7451): Timer 0 Buffer Register B * P_TMR0_TBRC (0x7452): Timer 0 Buffer Register C * P_TMR1_TBRA (0x7453): Timer 1 Buffer Register A * P_TMR1_TBRB (0x7454): Timer 1 Buffer Register B * P_TMR1_TBRC (0x7455): Timer 1 Buffer Register C B15 R 0 B14 R 0 B13 R 0 B12 R 0 TMRBUF B7 R 0 B6 R 0 B5 R 0 B4 R 0 TMRBUF B3 R 0 B2 R 0 B1 R 0 B0 R 0 B11 R 0 B10 R 0 B9 R 0 B8 R 0 B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
5.9.2.8. Timer 0 and 1 Input and Output Control Register
The P_TMRx_IOCtrl (x =0, 1) register controls the PWM output and input capture action type of TIOxA, TIOxB, and TIOxC (x = 0, 1) pins. By setting the CCLS and MODE bits in P_TMRx_Ctrl (x = 0, 1) register will determine the timer IO action mode. When choosing PWM output mode, the IOAMODE / IOBMODE / * P_TMR0_IOCtrl (0x7410): Timer 0 IO control register * P_TMR1_IOCtrl (0x7411): Timer 1 IO control register B15 R 0 B14 R 0 Reserved B7 R/W 0 B6 R/W 0 IOBMODE B5 R/W 0 B4 R/W 0 B3 R/W 0 B2 R/W 0 IOAMODE B13 R 0 B12 R 0 B11 R/W 0 B10 R/W 0 IOCMODE B1 R/W 0 B0 R/W 0 B9 R/W 0 B8 R/W 0 IOCMODE bits determines the waveform generation depending on the active clock edge. When choosing input capture mode, the IOAMODE/IOBMODE/IOCMODE bits defines the capture event including position detection changed.
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B15-B12 Reserved PWM compare match output mode 0000: Initial output 0, 0 output at 0001: Initial output 0, 1 output at compare match compare match B11-B8 IOCMODE Select Timer 0/Timer 1 IOC Configuration 01xx: Output hold Input capture mode 1000: Issue input capture interrupt 1001: Issue input capture interrupt at rising edge at both edges at falling edge Detection Register changes 101x: Issue input capture interrupt 11xx: Input capture when Position PWM compare match output mode 0000: Initial output 0, 0 output at 0001: Initial output 0, 1 output at compare match compare match B7-B4 IOBMODE Select Timer 0/Timer 1 IOB Configuration 01xx: Output hold Input capture mode 1000: 101x: Issue Issue input input capture capture 1001: Issue input capture compare match compare match 0010: Initial output 1, 0 output at 0011: Initial output 1, 1 output at compare match compare match 0010: Initial output 1, 0 output at 0011: Initial output 1, 1 output at
interrupt at rising edge interrupt at both edges
interrupt at falling edge 11xx: Input capture when Position Detection Register changes
PWM compare match output mode 0000: Initial output 0, 0 output at compare match 0010: Initial output 1, 0 output at compare match B3-B0 IOAMODE Select Timer 0/Timer 1 IOA Configuration 01xx: Output hold Input capture mode 1000: 101x: Issue Issue input input capture capture 1001: Issue input capture 0001: Initial output 0, 1 output at compare match 0011: Initial output 1, 1 output at compare match
interrupt at rising edge interrupt at both edges
interrupt at falling edge 11xx: Input capture when Position Detection Register changes
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5.9.2.9. Timer Start Register
The P_TMR_Start register selects the operation of counter start/stop for the P_TMRx_TCNT (x = 0 ~ 4). When counter operation stopped, its contents will be cleared. Set TMR0ST or * P_TMR_Start (0x7405): Timer Counter Start Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R 0 B6 R 0 Reserved B15-B5 B4 B3 B2 B1 B0 Reserved TMR4ST TMR3ST TMR2ST TMR1ST TMR0ST Timer 4 counter start setting Timer 3 counter start setting Timer 2 counter start setting Timer 1 counter start setting Timer 0 counter start setting 0: Counter operation stopped 0: Counter operation stopped 0: Counter operation stopped 0: Counter operation stopped 0: Counter operation stopped 1: Performs counting operation 1: Performs counting operation 1: Performs counting operation 1: Performs counting operation 1: Performs counting operation B5 R 0 B4 R/W 0 TMR4ST B3 R/W 0 TMR3ST B2 R/W 0 TMR2ST B1 R/W 0 TMR1ST B0 R/W 0 TMR0ST B11 R 0 B10 R 0 B9 R 0 B8 R 0 TMR1ST bit to 1 would start the P_TMR0_TCNT or P_TMR1_TCNT register immediately and vice versa.
5.9.2.10. Timer 0 and 1 Interrupt Enable Register
The P_TMRx_INT (x = 0, 1) register is used to enable or disable A/D conversion start request by TGRA compare match, interrupt requests for position detection changes, overflow/underflow of * P_TMR0_INT (0x7420): Timer 0 Interrupt Enable Register * P_TMR1_INT (0x7421): Timer 1 Interrupt Enable Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 TADSE B6 R/W 0 TCUIE B5 R/W 0 TCVIE B4 R/W 0 TPRIE B3 R 0 Reserved B2 R/W 0 TGCIE B1 R/W 0 TGBIE B11 R 0 B10 R 0 B9 R 0 B8 R/W 0 PDCIE B0 R/W 0 TGAIE TCNT, period register compare match and input capture/compare match of TGRA, TGRB, TGRC.
B15-B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Reserved PDCIE TADSE TCUIE TCVIE TPRIE Reserved TGCIE TGBIE TGAIE Timer General C Register interrupt enable bit Timer General B Register interrupt enable bit Timer General A Register interrupt enable bit 72 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable Feb. 16, 2006 Version: 1.1 Position detection change interrupt enable bit A/D conversion start request by TGRA enable bit Underflow interrupt enable bit Overflow interrupt enable bit Timer Period Register interrupt enable bit 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable
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5.9.2.11. Timer 0 and 1 Interrupt Status Register
The interrupt status register indicates the event generation of position detection changes, an underflow/overflow of TCNT, period register compare match and input capture/compare match of TGRA, TGRB, and TGRC. These flags show the interrupt sources. * P_TMR0_Status (0x7425): Timer 0 Interrupt Status Register * P_TMR1_Status (0x7426): Timer 1 Interrupt Status Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 TCDF B6 R/W 0 TCUIF B5 R/W 0 TCVIF B4 R/W 0 TPRIF
An interrupt would be generated when the corresponding interrupt enable bit is set in P_TMRx_INT (x = 0, 1) register. The TCDF represents the counter direction when timer is setup to center-aligned PWM mode or phase counting mode.
B11 R 0
B10 R 0
B9 R 0
B8 R/W 0 PDCIF
B3 R 0 Reserved
B2 R/W 0 TGCIF
B1 R/W 0 TGBIF
B0 R/W 0 TGAIF
B15-B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Reserved PDCIF TCDF TCUIF TCVIF TPRIF Reserved TGCIF TGBIF TGAIF Timer General C Register input capture/compare match flag Timer General B Register input capture/compare match flag Timer General A Register input capture/compare match flag 0: Input capture/compare match not occurred 0: Input capture/compare match not occurred 0: Input capture/compare match not occurred 1: Input capture/compare match has occurred 1: Input capture/compare match has occurred 1: Input capture/ compare match has occurred Position detection changes interrupt flag Timer Counter Count direction flag Timer Counter Underflow flag Timer Counter Overflow flag 0: Position no changed 0: Up-counting 0: Underflow not occurred 0: Overflow not occurred 1: Position changed 1: Down-counting 1: Underflow has occurred 1: Overflow has occurred 1: Compare match has occurred
Timer Period Register compare match flag 0: Compare match not occurred
: write `1' to clear this flag
5.9.2.12. Timer 0 and 1 Counter Register
The PDC timer has two TCNT counters (P_TMR0_TCNT and P_TMR1_TCNT), one for each channel. The TCNT counters are 16-bit readable registers that increment/decrement according to input clocks. Bits TMRPS in corresponding timer control register can select input clocks. P_TMR0_TCNT and P_TMR1_TCNT increment/decrement in center-aligned PWM mode, while they only increment in other modes. The TCNT counters are initialized to 0x0000 by compare matches with corresponding TGRA, TGRB, TGRC, or input captures to TGRA, TGRB, TGRC, or P_POSx_DectData (x = 0 , 1) data changes. When the TCNT counters overflow, a TCUIF flag in timer interrupt status register for the corresponding channel is set to 1. When TCNT underflows, a TUDIF flag in timer interrupt status register is set to 1.
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* P_TMR0_TCNT (0x7430): Timer 0 Counter Register * P_TMR1_TCNT (0x7431): Timer 1 Counter Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 TMRCNT B7 R 0 B6 R 0 B5 R 0 B4 R 0 TMRCNT B3 R 0 B2 R 0 B1 R 0 B0 R 0 B11 R 0 B10 R 0 B9 R 0 B8 R 0
5.9.3. Phase Counting Mode Operation
In phase counting mode, the phase difference between two external clock inputs is detected and timer counter counts up or down according to the clock phase relationship. This mode can be set for PDC0 and PDC1. The general application is for two-phase quadrature encoder pulse inputs. The clock source of PDC channel 0 utilizes TCLKA and TCLKB pins and PDC channel 1 utilizes TCLKC and TCLKD pins. The SPMC75F2413A supports the following four modes directional phase counting operation.
Figure 5-35 to Figure 5-38 represents the four-phase counting mode
useful for encoder equipped motor drive application. Table 5-12 shows phase counting mode 1 relationship. The phase resolution is amplified four times compared to encoder resolution specification (pulse / revolution). Figure 5-35 shows the example of phase counting 1. Table 5-12 phase counting mode 1 relationship TCLKA (PDC0) TCLKC (PDC1) H L Rising TCLKB (PDC0) TCLKD (PDC1) Rising Falling L H Falling Rising H L Down-count Counting Operation Up-count
operation, and Figure 5-39 shows the programming flowchart of phase counting mode procedure.
5.9.3.1. Phase Counting Mode 1
In phase counting mode 1, the P_TMRx_TCNT (x = 0, 1) always counts up as long as the TCLKB/TCLKD clock source is leading 90 degree with TCLKA/TCLKC. On the other hand, the P_TMRx_TCNT always count down when TCLKB/TCLKD clock source is lagging 90 degree with TCLKA/TCLKC. This mode is
Falling H L Rising Falling
Figure 5-35 phase counting mode 1
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5.9.3.2. Phase Counting Mode 2
In phase counting mode 2, the P_TMRx_TCNT (x = 0, 1) counting direction is determined by the logic level of TCLKB/TCLKD. When TCLKB/TCLKD remains logic `H' level, the counter does the up-counting operation. If TCLKB/TCKD is logic level `L', it does the down-counting operation. Table 5-13 shows the relationship. The counting operation is synchronous to the falling edge of TCLKA/TCLKC. Figure 5-36 shows the phase counting mode 2 examples.
Table 5-13 phase counting mode 2 relationship TCLKA (PDC0) TCLKC (PDC1) H L Rising Falling H L Rising Falling TCLKB (PDC0) TCLKD (PDC1) Rising Falling L H Falling Rising H L Counting Operation Up-count Down-count
Figure 5-36 phase counting mode 2
5.9.3.3. Phase Counting Mode 3
In phase counting mode 3, the P_TMRx_TCNT (x = 0, 1) does the up counting operation when TCLKB/TCLKD remains at logic level `H', and synchronous to the falling edge of TCLKA/TCLKC. On the other hand, the P_TMRx_TCNT (x = 0, 1) does the down counting operation in the situation of TCLKA/TCLKC at logic level `H', and synchronous to the falling edge of TCLKB/TCLKD. The following table shows the relationship and
Figure 5-37 represents this phase counting example.
Table 5-14 phase counting mode 3 relationship TCLKA (PDC0) TCLKC (PDC1) H L Rising Falling H L Rising Falling TCLKB (PDC0) TCLKD (PDC1) Rising Falling L H Falling Rising H L Counting Operation Up-count Down-count
Figure 5-37 phase counting mode 3
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5.9.3.4. Phase Counting Mode 4
In phase counting mode 4, the P_TMRx_TCNT counting direction is determined by the combinations of logic level and active level selection of TCLKx (x = A, B, C, D). When TCLKx (x = A, C) is at logic `H'/'L' level and TCLKy (y = B, D) clock is in the rising/falling edge, the counter will do the up counting operation. In the case of TCLKx (x = A, C) is at logic `H'/'L' level and TCLKy (y = B, D) clock is in the falling/rising edge; the counter will do the down counting operation. The following table shows the relationship and represents this phase counting example.
Table 5-15 phase counting mode 4 relationship TCLKA (PDC0) TCLKC (PDC1) H L Rising Falling H L Rising Falling TCLKB (PDC0) TCLKD (PDC1) Rising Falling L H Falling Rising H L Counting Operation Up-count Up-count Down-count Down-count
TCLKA (PDC0) TCLKC (PDC1)
TCLKB (PDC0) TCLKD (PDC1) Counting direction P_TMRx_Status.TCDF (x = 0, 1) 4 3 P_TMRx_TCNT (x = 0, 1) 1 2 3 2 1 0
Figure 5-38 phase counting mode 4
Phase counting operation
Descriptions: [1.] Enable phase counting mode by setting the
TCLKAEN/ TCLKBEN or TCLKCEN/ TCLKDEN in the
Enable phase counting
[1]
[2.]
P_IOA_SPE register. Select phase counting mode 1 to 4 by programming MODE bits in the P_TMRx_Ctrl (x = 0, 1) register.
Select phase counting type
[2]
[3.] Select the internal clock source FCK by choosing proper bit value TMRPS in the P_TMRx_Ctrl (x = 0, 1) register.
Select internal clock source
[3]
[4.] Start the counting operation with the bit TMR0ST or TMR1ST is set in P_TMR_Start register.
Start counter
[4]
Figure 5-39 Example programming flowchart of phase counting operation
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5.9.4. Position Detection Change (PDC) Mode Operation
The PDC timer has an extremely useful feature for position detection control used in BLDC motor driving application. The P_TMRx_TCNT (x = 0, 1) value can be transferred to TGRA, when CCLS bits is set to 100'b, 101'b or 110'b in the P_TMRx_Ctrl (x = 0, 1) register. Through the value of CCLS bits, the counter register can be stored to TGRA every six, three, one position detection data changes. Whenever the position detection changed event occurs, the counter register will be reset to 0x0000 after transferred to TGRA and PDCIF interrupt flag is set to 1. If the Through programming the bits value of SPLCNT, SPLCK and SPLMOD, user could avoid the noise on the hall signal inputs and position detection data register P_POS0_DectData, P_POS1_DectData can latch the correct position data. Figure 5-40 shows the programming flowchart of PDC mode operation. position detection interrupt enable bit PDCIE is set to 1 in the corresponding P_TMRx_INT (x = 0, 1) register, it would request a PDC interrupt to CPU.
PDC operation
Descriptions: [1.] Select the position data change is the clear source of counter register, the possible CCLS bits is 100'b, 101'b or 110'b in the P_TMRx_Ctrl (x = 0, 1) register. [2.] Set the counter clear edge is both edge of position signal. The CLEG is set to 11'b in the P_TMRx_Ctrl (x = 0, 1) register.
Select PDR as counter clear source
[1]
Setup counter clear edge
[2]
[3.] Select the PDR mode in P_TMRx_IOCtrl (x = 0, 1). The IOAMODE should set to 11xx'b.
Select input capture mode
[3]
[4.]
Enable the position detection logic by setting PDEN in the P_POSx_DectCtrl (x = 0, 1) register. Also configure proper bits value of SPLMOD and SPLCNT.
Enable position detection and setup bits value
[4]
[5.]
Enable
the
PDC
interrupt
by
setting
the
PDCIE
in
P_TMRx_INT (x =0, 1) register if necessary. [6.] Start the counting operation with the bit TMR0ST or TMR1ST is set in P_TMR_Start register.
Enable PDC interrupt
[5]
Start counter
[6]
Figure 5-40 Example programming flowchart of PDC operation
5.9.4.1. Timer 0 and 1 Position Detection Control Register
There are two position detection control registers available in SPMC75F2413A P_POS0_DectCtrl and P_POS1_DectCtrl are for timer 0 and timer 1, respectively. The control-registers control the sampling settings of position detection signals from TIOxA, TIOxB and TIOxC (x = 0, 1) input pins. The sampling parameters such as sampling clock, valid sampling count select, and sampling delay are all programmable. The SPLMOD bits determine the sampling position signal condition. They can be selected from three modessample when PWM on, sample regularly, or sample while low side transistors are in conducting current. The SPDLY bits select the sampling delay and used in modes where sampling is made while PWM is on or lower side phase are conducting current. It helps to prevent erroneous detection due to the glitch that occurs immediately after the transistor is on.
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IOB8/TIO0C IOB9/TIO0B IOB10/TIO0A SPCK P_POS0_DectCtrl. PDEN P_POS0_DectCtrl. SPLCK[1:0] P_POS0_DectCtrl. SPLMOD[1:0] P_POS0_DectCtrl. SPLCNT[3:0] Sampling counter 0 0 a 0 1 a
P_POS0_DectCtrl. SPDLY[6:0] Delay counter 6 0 Note1 P_TMR0_Status.PDCIF P_POS_DectData. PDR[2:0] P_TMR3_OutputCtrl. POLP Output active IOB5/TIO3A/U1 IOB5/TIO3A/V1 IOB5/TIO3A/W1 IOB2/TIO3D/U1N IOB1/TIO3E/V1N IOB0/TIO3F/W1N 3 1 2 3 4 5
6 6 Note2 6
4
Note1: If P_POS0_DectCtrl.SPLMOD=0, Delay Counter is cleared then starts counting if any output of TPM3 is active according to P_TMR3_OutputCtrl.POLP. Note2: The sampling circuit doest not work until Delay counter counts up to the number as P_POS0_DectCtrl.SPDLY.
Figure 5-41 Position detection with noise filter
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* P_POS0_DectCtrl (0x7462): Timer 0 Position Detection Control Register * P_POS1_DectCtrl (0x7463): Timer 1 Position Detection Control Register B15 R/W 0 SPLCK B7 R/W 0 PDEN B15-B14 SPLCK Sampling clock select 00: FCK/4 10: FCK/32 B13-B12 SPLMOD Sampling mode select 00: Start sampling when one B6 R/W 0 B5 R/W 0 B14 RW 0 B13 R/W 0 SPLMOD B4 R/W 0 B3 R/W 0 SPDLY 01: FCK/8 11: FCK/128 of 01: Sample immediately regardless of B2 R/W 0 B12 R/W 0 B11 R/W 0 B10 R/W 0 SPLCNT B1 R/W 0 B0 R/W 0 B9 R/W 0 B8 R/W 0
Ux/Vx/Wx/UxN/VxN/WxN (x=1,2) output is delay counter. active and delay counter count to the value of SPDLY 10: Start sampling when one of 11: Reserved UxN/VxN/WxN (x=1,2) output is active and delay counter count to the value of SPDLY B11-B8 B7 B6-B0 SPLCNT PDEN SPDLY Sampling count select Position detection enable Sampling delay The valid settings are from 1 to 15 times. Note that count 0 and 1 are assumed to be one time. 0: Disable 1: Enable
It is used to delay sampling in order to prevent erroneous detection due to noise that occurs immediately after any PWM output is active. The delay counter start counting when one of Ux/Vx/Wx/UxN/VxN/WxN (x=1,2) output is active.
5.9.4.2.
Timer 0 and 1 Position Detection Data Register
The sampling settings can be set in position detection control registers
The current filtered position data will be latched to these registers. P_POSx_DectCtrl (x = 0, 1).
* P_POS0_DectData (0x7464): Timer 0 Position Detection Data Register * P_POS1_DectData (0x7465): Timer 1 Position Detection Data Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R 0 B6 R 0 B5 R 0 Reserved B15-B13 B3-B0 Reserved PDR PDR[2]: Noise filtered position detection input from pin TIO0C PDR[1]: Noise filtered position detection input from pin TIO0B PDR[0]: Noise filtered position detection input from pin TIO0A B4 R 0 B3 R 0 B2 R 0 B1 R 0 PDR B0 R 0 B11 R 0 B10 R 0 B9 R 0 B8 R 0
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5.10. TPM TIMER 2 MODULE 5.10.1. Introduction
SPMC75F2413A has a general-purpose 16 bit TPM (Timer PWM Mode, TPM) timer that support functions of input capture and PWM output features. The timer 2 could be used to provide a time base system for speed loop of motor control applications. It has two timer input/output pins for input capture and PWM output operations. Figure 5-42 shows the block diagram of the timer 2 module. For details of timer 2 specifications, please refer to Table 5-16.
Figure 5-42 TPM timer 2 block diagram
Table 5-16 TPM Timer 2 Specification Function Clock sources Internal clock: External clock: TIO2A TIO2B P_TMR2_TGRA P_TMR2_TGRB P_TMR2_TBRA P_TMR2_TBRB P_TMR2_TPR P_TMR2_TCNT Internal clock: FCK/1, FCK/2, FCK/4, FCK/8 Rising Counting edge Falling Both edge Counter clear source Input capture function PWM compare match output function 1 output 0 output Output Hold Cleared on TIO2A, TIO2B capture input. Cleared on P_TMR2_TPR compare matches. Yes Yes Yes Yes 80 Feb. 16, 2006 Version: 1.1 TPM Timer 2 FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024 TCLKA, TCLKB
IO pins Timer general register Timer buffer register Timer period and counter register Capture sample clock
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Function Edge-aligned PWM Center-aligned PWM Timer buffer operation AD convert start trigger Interrupt sources Yes Yes Yes P_TMR2_TGRA compare match Timer 2 TPR interrupt Timer 2 TGRA interrupt Timer 2 TGRB interrupt
TPM Timer 2
5.10.2. TPM Timer 2 Counting Operation
The TPM2 is a general-purpose timer with input capture and PWM compare match output capability. TPM timer 2 provided independent time base at different input clock sources for application such as The sampling and constant frequency driven features for digital control system. Speed loop time base of inverter motor control system. Timer mode operation Count on external clock input pin TCLKA or TCLKB Edge-aligned PWM mode (continuous up counting, PWM output mode) Center-aligned PWM mode (continuous up/down counting, PWM output mode) At edge-aligned PWM mode, user must set P_TMR2_TPR period register and P_TMR2_TGRx (x = A, B) general register then set counter clear source (CCLS) as cleared by timer period compare match. The compare match output condition set at P_TMR2_IOCtrl register.
Figure 5-44 shows the normal continuous up counting mode for
interrupt when TGAIE or TGBIE bit is set in the corresponding timer interrupt enable register. The initial value of P_TMR2_TPR can be any value from 0x0000 to 0xFFFF. Either the external clock input pin or internal clock source FCK can be selected as the clock source of the timer. The normal continuous up counting mode is extremely suitable for the generation of edge-triggered or asynchronous PWM waveforms and sampling periods in digital motor control systems.
Figure 5-43 shows the normal continuous up counting mode of the
TPM timer 2.
5.10.2.1. Continuous Up Counting Mode with Edge-Aligned PWM
The TPM timer 2 can be configured as edge-aligned PWM mode by setting MODE bits in P_TMR2_Ctrl. At this mode, the timer counter act as up-counting timer and counting from 0x0000 to timer period register value. User must set P_TMR2_TPR register and set counter clear source (CCLS) is cleared by timer period compare match. The timer continuous up counting according to the input clock sources from bits value TMRPS defined in corresponding timer control register. The timer counter register will be cleared to zero when the register value matches that of the timer period register and period compare match event interrupt flag TPRIF is set. The period interrupt request is generated when PPRIE bit is set in P_TMR2_INT register. The general register compare match event occurs when timer counter register matches the content of TGRA or TGRB register. It generates the general register compare match
edge-aligned PWM generation of timer 2. The TPM timer 2 module can perform PWM compare match output function up to two pins output. The output waveforms have active low at compare match, active high at compare match and output hold for the corresponding TIO2A and TIO2B output pin using compare match with P_TMR2_TGRA and P_TMR2_TGRB register respectively. Figure 5-45 shows the programming flowchart of PWM compare match output operation. Figure 5-46 is an example of edge aligned PWM. The correlations between the configuration of P_TMR2_IOCtrl and PWM output, the register TGRx and interrupt status flag TGxIF(x=A, B) are shown, respectively.
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Figure 5-43 Continuous up counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b)
Figure 5-44 Edge-Aligned mode PWM
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Compare match output operation
Descriptions: [1.] Setup the TGRA/TGRB value to generate the desired waveform width.
Setup TGR register value
[1]
[2.] Setup the CCLS bits to 111'b so that period register determines the period and counter clear source,
Setup period and counter clear source
[2]
[3.]
Set the bits TIO2AEN and TIO2BEN, to 1 in the P_IOA_SPE register and configures the corresponding IO pin to output mode.
Enable timer special function
[3]
[4.] Select compare match output mode through P_TMR2_IOCtrl register.
Select waveform output type
[4]
[5.]
Start the counting operation with the bit TMR2ST is set in P_TMR_Start register.
Start counter
[5]
Figure 5-45 Example programming flowchart of PWM compare match output operation
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P_TMR2_TGRA[15:0] P_TMR2_TGRB[15:0] P_TMR2_TPR[15:0] P_TMR2_TCNT[15:0] P_TMR2_Status .TCDF P_TMR2_Status .TPRIF P_TMR2_Status .TGAIF 0
2 7 F 123456789ABCDEF0123456789ABCDEF01
Write TMR2_Status.TGAIF=1 to clear this flag
P_TMR2_Status .TGBIF P_IOA_SPE[15:0] 6000 Write P_IOA_Dir to configure IOs of special function as otuput P_IOA_Dir[15:0] P_TMR2_IOCtrl[15:0] 6000 12
IOA9/TIO2A
IOA10/TIO2B P_TMR0_IOCtrl = 12: 1. IOA as initial 1 output, 0 output at compare match 2. IOB as initial 0 output, 1 output at compare match
Figure 5-46 TMR2 edge aligned PWM
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5.10.2.2. Timer mode Operation
The Timer mode can be selected by setting MODE in P_TMR2_Ctrl. Except output waveform, it operates the same as continuous up counting mode with edge-aligned PWM. The first compare match event of general register occurs when timer counter register matches the content of TGRA or TGRB register and the output will transits in the way set by IOAMODE, IOBMODE, respectively. If compare match event occurs again, the compare match interrupt flag will be set but output waveform retain. Figure 5-47 shows the output timing in Timer mode.
P_TMR2_TCNT[15:0] P_TMR2_Status .TCDF P_TMR2_Status .TPRIF P_TMR2_Status .TGAIF
0
123456789ABCDEF0123456789ABCDEF01
Write TMR2_Status.TGAIF=1 to clear this flag
P_TMR2_Status .TGBIF P_IOA_SPE[15:0] 6000 Write P_IOA_Dir to configure IOs of special function as otuput P_IOA_Dir[15:0] P_TMR2_IOCtrl[15:0] 6000 12
IOA9/TIO2A
IOA10/TIO2B
P_TMR0_IOCtrl = 12: 1. IOA as initial 1 output, 0 output at compare match 2. IOB as initial 0 output, 1 output at compare match
Figure 5-47 Timer mode output timing
5.10.2.3. Continuous up/down counting mode with Center-Aligned PWM
The operation of continuous up/down counting mode is the same as up counting mode except the timer period register defines the middle transition point of whole counting process. The counting direction changes from up to down when the timer counter register reaches the timer period register. The period of the timer is two times of P_TMR2_TPR of the scaled clock input and the setting of CKEGS in the P_TMR2_Ctrl register. Figure 5-48 shows the continuous up/down counting mode operation.
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Figure 5-48 Continuous up/down counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b)
The initial value of the timer period register can be any value from 0x0000 to 0xFFFF. When the value of the timer counter register equals to timer period register, the TPM timer 2 start to count down to zero. The period interrupts behaves the same manner as described in the continuous up counting mode. The counting direction is recorded at TCDF bit in the P_TMR2_Status register. Either the external clock input pin or
internal clock source FCK can be selected as the clock source of the timer. Figure 5-49 shows the center-aligned mode PWM at continuous up/down counting mode of timer 2. Figure 5-50 is an example of center aligned PWM. The correlations between the configuration of P_TMR2_IOCtrl and PWM output, the register TGRx and interrupt status flag TGxIF(x=A, B) are shown, respectively.
Figure 5-49 Center-Aligned mode PWM
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P_TMR2_TGRA[15:0] P_TMR2_TGRB[15:0] P_TMR2_TPR[15:0] P_TMR2_TCNT[15:0] P_TMR2_Status .TCDF P_TMR2_Status .TPRIF P_TMR2_Status .TGAIF 0
2 7 F 123456789ABCDEFEDCBA9876543210123
Write TMR2_Status.TGAIF=1 to clear this flag
P_TMR2_Status .TGBIF P_IOA_SPE[15:0] 6000 Write P_IOB_Dir to configure IOs of special function as otuput P_IOA_Dir[15:0] P_TMR2_IOCtrl[15:0] 6000 21
IOA9/TIO2A IOA10/TIO2B P_TMR0_IOCtrl = 21: 1. IOA as initial 0 output, 1 output at compare match 2. IOB as initial 1 output, 0 output at compare match
Figure 5-50 TMR2 center aligned PWM
5.10.2.4. Input Capture Operation
The capture function activation and the input edge at which the interrupt status flag issued are determined by the bits of IOAMODE and IOBMODE in the P_TMR2_IOCtrl register, respectively. It can be the rising edge, falling edge or both edge. The value of counter is always transferred to TGRx (x=A, B) and TBRx (x=A, B) at the rising and falling edge of corresponding input capture port, respectively. The counter register, P_ TMR2_TCNT can be cleared according to the setting of CCLS in P_TMR2_Ctrl register. The counter clear source can be one of TIO0A and TIO0B at the selected edge according to CLEGS in P_TMR2_Ctrl. Table 5-17 shows the input capture configurations settings and results. When the input capture function is selected, the pulse width or period can be measured presents on input pin. Figure 5-52 shows the programming flowchart of input capture operation. Figure 5-53 is an example of input capture TIO0x (x=A, B). The correlations between the configuration of P_TMR2_IOCtrl and interrupt even are shown.
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Figure 5-51 input capture signal connected to TIO2A
Table 5-17 input capture configuration settings and results Input capture settings CLEGS Rising edge Rising edge Rising edge Falling edge Falling edge Falling edge Both edge Both edge Both edge CCLS TIO2A TIO2A TIO2A TIO2A TIO2A TIO2A TIO2A TIO2A TIO2A IOAMODE Rising edge Falling edge Both edge Rising edge Falling edge Both edge Rising edge Falling edge Both edge Counter cleared at rising edge, interrupt at rising edge Counter cleared at rising edge, interrupt at falling edge Counter cleared at rising edge, interrupt at both edge Counter cleared at falling edge, interrupt at rising edge Counter cleared at falling edge, interrupt at falling edge Counter cleared at falling edge, interrupt at both edge Counter cleared at both edge, interrupt at rising edge Counter cleared at both edge, interrupt at falling edge Counter cleared at both edge, interrupt at both edge P_TMR2_TGRA = period (40 ms) P_TMR2_TBRA = T1 (25ms) P_TMR2_TGRA = period (40 ms) P_TMR2_TBRA = T1 (25ms) P_TMR2_TGRA = period (40 ms) P_TMR2_TBRA = T1 (25ms) P_TMR2_TGRA = T2 (15 ms) P_TMR2_TBRA = period (40ms) P_TMR2_TGRA = T2 (15 ms) P_TMR2_TBRA = period (40ms) P_TMR2_TGRA = T2 (15 ms) P_TMR2_TBRA = period (40ms) P_TMR2_TGRA = T2 (15 ms) P_TMR2_TBRA = T1 (25ms) P_TMR2_TGRA = T2 (15 ms) P_TMR2_TBRA = T1 (25ms) P_TMR2_TGRA = T2 (15 ms) P_TMR2_TBRA = T1 (25ms) Description Results
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Input capture operation
Descriptions: [1.] Select TIO2A or TIO2B as counter clear source, and then write value to CCLS bits in P_TMR2_Ctrl register.
Select TGR as counter clear source
[1]
[2.] [3.]
Setup the counter clear edge by configuring CLEGS: Select capture input interrupt edge as rising, falling, or both edge with setting of bits IOxMOD (x = A, B).
Setup counter clear edge
[2]
[4.]
Enable capture interrupt in P_TMR2_INT register if necessary. Start the counting operation with the bit TMR2ST set in P_TMR_Start register.
Select capture detection edge
[3]
[5.]
Enable capture interrupt
[4]
Start counter
[5]
Figure 5-52 Example programming flowchart of input capture operation
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P_TMR2_TCNT[15:0] P_TMR2_TGRA[15:0] P_TMR2_TGRB[15:0] P_TMR2_TBRA[15:0] P_TMR2_TBRB[15:0] P_TMR2_Status .TGAIF P_TMR2_Status .TGBIF 0
3E 0 0
81
c3
0
1
2 C3 C3
0 3E
Deglitch delay 0 98 Capture P_TMR2_TCNT to P_TMR2_TBRx when falling edge Capture P_TMR2_TCNT to P_TMR2_TGRx when rising edge
P_IOA_Dir[15:0] P_TMR2_IOCtrl[15:0]
IOA9/TIO2A IOA10/TIO2B Note: 1. Write P_TMR2_Ctrl.CCLS[2:0] to select IOA9/TIO2A capture input as the clear source of P_TMR2_TCNT 2. Write P_TMR2_Ctrl.CLEGS[1:0] to select rising edge to clear P_TMR2_TCNT
P_TMR0_IOCtrl = 98: 1. Issue capture interrupt at rising edge of IOA9/TIO2A 2. Issue capture interrupt at falling edge of IOA10/TIO2B
Figure 5-53 Capture input signal width and cycle
5.10.2.5. Timer 2 Control Registers
The P_TMR2_Ctrl configures the selection of timer clock source, counter clock edge, counter clear source, counter clear edge, and capture input sample clock and timer operating modes. TCLKA, * P_TMR2_Ctrl (0x7402): Timer 2 Control Register B15 R/W 0 SPCK B7 R/W 0 B6 R/W 0 CCLS B5 R/W 0 B4 R/W 0 CKEGS B14 R/W 0 B13 R/W 0 B12 R/W 0 MODE B3 R/W 0 B2 R/W 0 B1 R/W 0 TMRPS B11 R/W 0 B10 R/W 0 B9 R/W 0 CLEGS B0 R/W 0 B8 R/W 0 TCLKB clock input will be sampled by system clock FCK. When programmed at counting on both edge, the input clock is halved. Any pulse narrower than four sampling clocks will be ignored.
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B15-B14
SPCK
Capture input sample clock select
00: FCK/1 10: FCK/4 0xxx: Timer mode 1x1x: Center-aligned PWM mode
01: FCK/2 11: FCK/8 1x0x: Edge-aligned PWM mode
B13-B10
MODE
Modes select
B9-B8
CLEGS
Counter clear edge in 00: do not clear input capture mode 10: falling edge 000: TCNT clearing disabled 010: TCNT cleared by TIO2B capture input 100: Reserved 110: Reserved
01: rising edge 11: both edge 001: TCNT cleared by TIO2A capture input 011: Reserved 101: Reserved 111: TCNT cleared by P_TMR2_TPR compare match
B7-B5
CCLS
Counter clear source select
B4-B3
CKEGS
Clock edge select
00: Count at rising edge 1X: Count at both edges
01: Count at falling edge
B2-B0
TMRPS
Timer pre-scalar select
000: Counts on FCK /1 010: Counts on FCK /16 100: Counts on FCK /256 110: Counts on TCLKA pin input
001: Counts on FCK /4 011: Counts on FCK /64 101: Counts on FCK /1024 111: Counts on TCLKB pin input
5.10.2.6. Timer 2 Period Register
The P_TMR2_TPR is a 16-bit readable/writable register. used to set the period of PWM waveform. It is MODE bits programmed in P_TMR2_Ctrl value is 0xFFFF. at 0x0000. register. Its default When P_TMR2_TCNT When P_TMR2_TPR register is set to 0x0000,
register reaches P_TMR2_TPR register value, P_TMR2_TCNT register will be cleared to 0x0000 (up-counting mode) or start down-count (continuous up-/down-counting mode) according to * P_TMR2_TPR (0x7437): Timer 2 Period Register B15 R/W 1 B14 R/W 1 B13 R/W 1 B12 R/W 1
the P_TMR2_TCNT register counter will stop counting and remain
B11 R/W 1 TMRPRD
B10 R/W 1
B9 R/W 1
B8 R/W 1
B7 R/W 1
B6 R/W 1
B5 R/W 1
B4 R/W 1 TMRPRD
B3 R/W 1
B2 R/W 1
B1 R/W 1
B0 R/W 1
5.10.2.7. Timer 2 General and Buffer Register
TGRA, TGRB are 16-bit registers. The TPM timer 2 has two timer general registers. The TGR registers are dual function 16-bit readable/writable registers, functioning as either PWM compare match or input capture registers. The values in TGR and TCNT are constantly compared with each other when the TGR registers are used as PWM compare match output registers. When the both values match, the TGAIF or TGBIF bit in corresponding timer interrupt status register is set to 1. Compare match outputs can be selected by TIO2A and TIO2B. (c) Sunplus Innovation Technology Inc. Proprietary & Confidential 91 The timer buffer registers TBRA and TBRB are the double buffers of TGRA and TGRB, respectively. The value of TGRx (x=A, B) Feb. 16, 2006 Version: 1.1 When PWM mode, edge-aligned PWM mode, or center-aligned PWM mode is selected, the TGR register behaves as the duty ratio value register. Upon reset, the TGR registers are initialized to 0x0000. When the TGR registers are used as input capture registers, the TCNT value is stored at the rising edge of input capture port.
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can automatically be updated when the period compare match event occurs. That is, the duty ratio value will not be updated until one period ends completely. When the TBR registers are used as * P_TMR2_TGRA (0x7446): Timer 2 General Register A * P_TMR2_TGRB (0x7447): Timer 2 General Register B B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0
input capture registers, the TCNT value is stored at the falling edge of input capture port.
B11 R/W 0 TMRGLR
B10 R/W 0
B9 R/W 0
B8 R/W 0
B7 R/W 0
B6 R/W 0
B5 R/W 0
B4 R/W 0 TMRGLR
B3 R/W 0
B2 R/W 0
B1 R/W 0
B0 R/W 0
* P_TMR2_TBRA (0x7456): Timer 2 Buffer Register A * P_TMR2_TBRB (0x7457): Timer 2 Buffer Register B B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 TMRBUF B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 TMRBUF B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
5.10.2.8. Timer 2 Input and Output Control Register
The P_TMR2_IOCtrl register controls the PWM compare match output and input capture action type of TIO2A and TIO2B pins. By setting the CCLS and MODE bits in P_TMR2_Ctrl register will determine the timer IO action mode. When choosing PWM * P_TMR2_IOCtrl (0x7412): Timer 2 IO control register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 B6 R/W 0 IOBMODE B15-B8 B7-B4 Reserved IOBMODE Select Timer 0/Timer 1 IOB Configuration PWM compare match output mode 0000: Initial output 0, 0 output at 0001: Initial output 0, 1 output at compare match compare match B5 R/W 0 B4 R/W 0 B3 R/W 0 B2 R/W 0 IOAMODE B1 R/W 0 B0 R/W 0 B11 R 0 B10 R 0 B9 R 0 B8 R 0 compare match output mode, the IOAMODE/IOBMODE bits determines the waveform generation depending on the active clock edge. When choosing input capture mode, the IOAMODE/IOBMODE bits defines the capture event.
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0010: Initial output 1, 0 output at 0011: Initial output 1, 1 output at compare match 01xx: Output hold Input capture mode 1000: Issue input capture interrupt 1001: Issue input capture interrupt at rising edge at both edges at falling edge Detection Register changes 101x: Issue input capture interrupt 11xx: Input capture when Position PWM compare match output mode 0000: Initial output 0, 0 output at 0001: Initial output 0, 1 output at compare match compare match B3-B0 IOAMODE Select Timer 0/Timer 1 IOA Configuration 01xx: Output hold Input capture mode 1000: Issue input capture interrupt 1001: Issue input capture interrupt at rising edge at both edges at falling edge Detection Register changes 101x: Issue input capture interrupt 11xx: Input capture when Position compare match compare match 0010: Initial output 1, 0 output at 0011: Initial output 1, 1 output at compare match
5.10.2.9. Timer 2 Start Register
The P_TMR_Start register selects the operation of counter start/stop for the P_TMRx_TCNT (x = 0 ~ 4). When counter operation stopped, its contents will be cleared. Set TMR2ST bit to * P_TMR_Start (0x7405): Timer Counter Start Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R 0 B6 R 0 Reserved B15-B5 B4 B3 B2 B1 B0 Reserved TMR4ST TMR3ST TMR2ST TMR1ST TMR0ST Timer 4 counter start setting Timer 3 counter start setting Timer 2 counter start setting Timer 1 counter start setting Timer 0 counter start setting 0: Counter operation stopped 0: Counter operation stopped 0: Counter operation stopped 0: Counter operation stopped 0: Counter operation stopped 1: Performs counting operation 1: Performs counting operation 1: Performs counting operation 1: Performs counting operation 1: Performs counting operation B5 R 0 B4 R/W 0 TMR4ST B3 R/W 0 TMR3ST B2 R/W 0 TMR2ST B1 R/W 0 TMR1ST B0 R/W 0 TMR0ST B11 R 0 B10 R 0 B9 R 0 B8 R 0 1 would start the P_TMR2_TCNT register immediately and vice versa.
5.10.2.10. Timer 2 Interrupt Enable Register
The P_TMR2_INT register is used to enable or disable A/D conversion start request by TGRA compare match, interrupt requests for period register compare match and input capture/compare match of TGRA or TGRB.
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* P_TMR2_INT (0x7422): Timer 2 Interrupt Enable Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 TADSE B15-8 B7 B6-B5 B4 B3-B2 B1 B0 Reserved TADSE Reserved TPRIE Reserved TGBIE TGAIE Timer General B Register interrupt enable bit Timer General A Register interrupt enable bit 0: Disable 0: Disable 1: Enable 1: Enable Timer Period Register interrupt enable bit 0: Disable 1: Enable A/D conversion start request by TGRA enable bit 0: Disable 1: Enable B6 R 0 Reserved B5 R 0 B4 R/W 0 TPRIE B3 R 0 Reserved B2 R 0 B1 R/W 0 TGBIE B0 R/W 0 TGAIE B11 R 0 B10 R 0 B9 R 0 B8 R 0
5.10.2.11. Timer 2 Interrupt Status Register
The interrupt status register indicates the event generation of a period registers compare match and input capture/compare match of TGRA or TGRB. These flags show the interrupt sources. An interrupt would be generated when the corresponding interrupt * P_TMR2_Status (0x7427): Timer 2 Interrupt Status Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 TCDF B15-8 B7 B6-B5 B4 B3-B2 B1 B0 Reserved TCDF Reserved TPRIF Timer Period Register compare match flag 0: Compare match not occurred Reserved TGBIF TGAIF Timer General B Register input capture/compare match flag Timer General A Register input capture/compare match flag
: write `1' to clear this flag
enable bit is set in P_TMR2_INT register. The TCDIF represents the counter direction when timer is setup to center-aligned PWM mode.
B11 R 0
B10 R 0
B9 R 0
B8 R 0
B6 R 0 Reserved
B5 R 0
B4 R/W 0 TPRIF
B3 R 0 Reserved
B2 R 0
B1 R/W 0 TGBIF
B0 R/W 0 TGAIF
Timer Count direction flag
0: Up-counting
1: Down-counting
1: Compare match has occurred
0: Input capture/compare match not occurred 0: Input capture/compare match not occurred
1: Input capture/compare match has occurred 1: Input capture/compare match has occurred
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5.10.2.12. Timer 2 Counter Register
The TPM timer 2 has a 16 bit counter P_TMR2_TCNT register. It is a readable register that increments/decrements according to input clocks. Bits TMRPS in corresponding timer control register can select input clocks. P_TMR2_TCNT can increment or decrement in center-aligned PWM mode, although they only increment in other modes. The P_TMR2_TCNT register is reset to 0x0000 by compare matches with corresponding TGRA, TGRB or input captures to TGRA, TGRB. * P_TMR2_TCNT (0x7432): Timer 2 Counter Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 TMRCNT B7 R 0 B6 R 0 B5 R 0 B4 R 0 TMRCNT B3 R 0 B2 R 0 B1 R 0 B0 R 0 B11 R 0 B10 R 0 B9 R 0 B8 R 0
5.11. MCP TIMER 3 AND 4 MODULE 5.11.1. Introduction
There are two channels of 16bit MCP (Motor Control PWM) timers, MCP timer 3 and MCP timer 4 on the SPMC75F2413A chip. The MCP timers provide two independent set of full function for three-phase, six programmable PWM waveform output capabilities. The MCP timer 3 should work with PDC timer 0 and MCP timer 4 works with PDC timer 1 to form the speed closed loop control for BLDC and ACI motor applications. This MCP timer module has totally twelve timer output pins for motor control operations. Figure
5-54 shows the block diagram of the MCP timer 3 and 4 module.
For details of timer specifications, please refer to Table 5-18.
FCK/4 FCK/16 FCK/64 FCK/256 FCK/1024 TCLKA TCLKB FCK
CLR SET SET
D
Q Q
FCK
D
Q
Up_Down
CLR
Q
Up_phase Down_phase FCK
Counter Logic
16 Bit Counter
TMRPS
System Reset
System Reset
Figure 5-54 MCP timer 3 and 4 block diagram
Table 5-18 MCP timer 3 and 4 specification Function Clock sources MCP Timer 3 Internal clock: External clock: TIO3A/U1 Output pins TIO3B/V1 TIO3C/W1 (c) Sunplus Innovation Technology Inc. Proprietary & Confidential 95 MCP Timer 4 FCK/1, FCK/4, FCK/16, FCK/64, FCK/256, FCK/1024 TCLKA, TCLKB TIO4A/U2 TIO4B/V2 TIO4C/W2 Feb. 16, 2006 Version: 1.1
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Function
MCP Timer 3 TIO3D/U1N TIO3E/V1N TIO3F/W1N P_TMR3_TGRA P_TMR3_TGRB P_TMR3_TGRC P_TMR3_TGRD P_TMR3_TBRA
MCP Timer 4 TIO4D/U2N TIO4E/V2N TIO4F/W2N P_TMR4_TGRA P_TMR4_TGRB P_TMR4_TGRC P_TMR4_TGRD P_TMR4_TBRA P_TMR4_TBRB P_TMR4_TBRC
Timer general register
Timer buffer register Interrupt period Counting edge Counter clear source PWM compare match output function 1 output 0 output Output Hold
P_TMR3_TBRB P_TMR3_TBRC Interrupt every one, two, four and eight period Rising Falling Both edge Clear on P_TMR3_TPR compare match Yes Yes Yes Yes Yes Yes Yes Yes Yes, but not P_TMR3_TGRD P_TMR3_TGRD compare match Yes, through P_TMR_LDOK register Yes, through P_TMR_Output register Yes Yes Yes Yes P_POS0_DectData register change P_TMR3_TGRB compare match P_TMR3_TGRC compare match
Clear on P_TMR4_TPR compare match Yes Yes Yes Yes Yes Yes Yes Yes Yes, but not P_TMR4_TGRD P_TMR4_TGRD compare match Yes, through P_TMR_LDOK register Yes, through P_TMR_Output register Yes Yes Yes Yes P_POS1_DectData register change P_TMR4_TGRB compare match P_TMR4_TGRC compare match general register Yes, through P_TPWM_Write register FTIN2 OL2
BLDC motor drive PWM ACI motor drive PWM Edge-aligned PWM Center-aligned PWM Complementary PWM Timer buffer operation AD convert start trigger PWM duty partial load prevention PWM output enable control PWM waveform control Forced H Forced L Active H Active L
UVW phase synchronization
Duty Mode MCP registers write protection External fault input pin External overload input pin
Use P_TMR3_TGRA register or thee timer Use P_TMR4_TGRA register or thee timer general register Yes, through P_TPWM_Write register FTIN1 OL1 Timer 3 TPR interrupt Timer 3 TGRA interrupt
Timer 4 TPR interrupt Timer 4 TGRA interrupt MCP4 external fault input 2 interrupt External overload input 2 interrupt MCP4 PWM output short interrupt
Interrupt source
External fault input 1 interrupt External overload input 1 interrupt MCP3 PWM output short interrupt
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5.11.2. MCP Timer 3 and 4 Counting Operation
The on-chip MCP timer 3 and 4 have the following five possible counting operations Timer mode operation. Count on external clock input pin TCLKA or TCLKB. Edge-aligned PWM mode (continuous up counting, PWM output mode). Center-aligned PWM mode (continuous up/down counting, PWM output mode). Complementary PWM mode w/o dead-time control. The initial value of P_TMRx_TPR (x = 3, 4) can be any value from 0x0000 to 0xFFFF. Either the external clock input pin or internal clock source FCK can be selected as the clock source of the timer. The normal continuous up counting mode is extremely suitable for the generation of edge-triggered or asynchronous PWM timer control register. The timer counter register will be cleared to zero when the register value matches that of the timer period register and period compare match event interrupt flag TPRIF is set. The period interrupt request is generated when PPRIE bit is set in P_TMRx_INT (x = 3, 4) register.
5.11.2.1. Continuous Up Counting Mode with Edge-Aligned PWM
Each MCP timer channel can be configured as edge-aligned PWM mode by setting MODE bits in P_TMR0_Ctrl. At this mode, the timer counter act as up-counting timer and counting from 0x0000 to timer period register value. User must set P_TMRx_TPR (x = 3 ~ 4) register and set counter clear source (CCLS) as cleared by timer period compare match and also needs to setup proper bits value of PRDINT in the P_TMRx_Ctrl (x = 3, 4) register. The MCP timer continuous up counting according to the input clock sources from bits value TMRPS defined in corresponding
waveforms and sampling periods in digital motor control systems. Figure 5-55 shows the normal continuous up counting mode of the MCP timer 3.
At edge-aligned PWM mode, user must configure P_TMRx_TPR (x= 3, 4) period register and P_TMRx_TGRy (y = A, B, C) general register, then set counter clear source (CCLS) as cleared by timer period compare match. The output conditions of compare match are configured by setting P_TMRx_IOCtrl (x= 3, 4) register.
Figure 5-56 shows the normal continuous up counting mode for edge-aligned PWM generation of timer 3.
P_TMR3_TPR = 8 8 7 P_TMR3_TPR = 5 5 4 3 2 1 P_TMR3_TCNT 0 0 1 0 2 1 3 2 4 3 P_TMR3_TPR = 5 5 4 5 6
Counter clock source
Figure 5-55 Continuous up counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b)
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Figure 5-56 Edge-Aligned mode PWM
5.11.2.2. Timer mode Operation
The Timer mode can be selected by setting MODE in P_TMRx_Ctrl (x=3, 4). Except output waveform, it operates the same as continuous up counting mode with edge-aligned PWM. The first compare match event of general register occurs when timer counter register matches the content of TGRA, TGRB or TGRC register and the output will transits in the way set by IOAMODE, IOBMODE and IOCMODE, respectively. If compare match event occurs again, the compare match interrupt flag will be set but output waveform retain.
5.11.2.3. Continuous up/down counting mode with Center-Aligned PWM
The operation of continuous up/down counting mode is the same as up counting mode except the timer period register defines the middle transition point of the whole counting process. The counting direction changes from up to down when the timer counter register reaches the timer period register. The period of the timer is two times of P_TMRx_TPR (x = 3, 4) of the scaled clock input and the setting of CKEGS in the P_TMRx_Ctrl (x = 3, 4) register. Figure 5-57 shows the continuous up/down counting mode operation.
P_TMRx_TPR = 5 5 4 3 2 1 P_TMRx_TCNT 0 4 3 2 1 0 1 2 P_TMRx_TPR = 3 3 2 1 0 1 2 P_TMRx_TPR = 3 3 2 1
Counter clock source
Figure 5-57 Continuous up/down counting example (CCLS = 111'b, CKEGS = 00'b, TMRPS = 000'b)
The initial value of the timer period register can be any value from 0x0000 to 0xFFFF. When the value of the timer counter register equals to timer period register, the MCP timer start to count down to zero. The period interrupt behaves the same manner as described in the continuous up counting mode.
The counting direction is recorded at TCDF bit in the P_TMRx_Status (x = 3, 4) register. Either the external clock input pin or internal clock source FCK can be selected as the clock source of the timer. Figure 5-58 shows the center-aligned mode PWM at continuous up/down counting mode of timer 3.
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P_TMR3_TPR = 5 5 4 3 2 1 P_TMR3_TCNT 0 4 3 2 1 0 1 2 P_TMR3_TPR = 3 3 2 1 0 1 2 P_TMR3_TPR = 3 3 2 1
Counter clock source Active High P_TMR3_IOCtrl.IOAMODE = 0x01 TIO3A pin Active Low P_TMR3_IOCtrl.IOAMODE = 0x02
Figure 5-58 Center-Aligned mode PWM
5.11.2.4. Timer/PWM Module Write Enable Control Register
User must write 0x5A01 to P_TPWM_Write register to enable the timer 3 and write 0x5A02 to P_TPWM_Write to enable timer 4 for timer PWM generation. The P_TPWM_Write register provides a way to prevent the settings of timer 3 or 4 being miswritten due to CPU runaway. To modify the setting of timer 3 or timer 4, the Registers corresponding TMR3/4WE bit must be set to `1'. TMR3WE bit controls the write operation of following registers P_TMR3_Ctrl, P_TMR3_IOCtrl, P_TMR3_INT, P_TMR3_Status, P_TMR3_DeadTime, P_TMR_Start, P_TMR_Output TMR4WE bit controls the write operation of following registers P_TMR4_Ctrl, P_TMR4_IOCtrl, P_TMR4_INT, P_TMR4_Status, P_TMR4_DeadTime, P_TMR_Start, P_TMR_Output The TMR3WE and TMR4WE control the MCP registers respectively as follows:
concerned with TMR3WE and TMR4WE are listed below. The recommended procedure of P_TPWM_Write register is first to read the content then does logical OR operation on control words (0x5A01 or 0x5A02). Write back the result to P_TPWM_Write last.
* P_TPWM_Write (0x7409): Timer/PWM Module Write Enable Control Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R 0 B6 R 0 B5 R 0 Reserved B15-8 WECHK Write enable check bits pattern. To properly enable TMR4WE and TMR3WE, these bits must be written to `0x5A'. Otherwise, the control bits will not be set. These bits will be read as `0'. B7-2 B1 B0 Reserved TMR4WE TMR3WE Timer 4 setting registers write enable select bit Timer 3 setting registers write enable select bit 0: Disable 0: Disable 1: Enable 1: Enable B4 R 0 B3 R 0 B2 R 0 B1 R/W 0 TMR4WE B0 R/W 0 TMR3WE B11 R 0 B10 R 0 B9 R 0 B8 R 0
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5.11.2.5. Timer 3 and 4 Control Registers
The P_TMRx_Ctrl (x = 3, 4) configures the selection of timer clock source, counter clock edge, counter clear source, counter clear edge, TPR interrupt frequency and timer operating modes. TCLKA, TCLKB clock input will be sampled by system clock FCK. Any * P_TMR3_Ctrl (0x7403): Timer 3 Control Register * P_TMR4_Ctrl (0x7404): Timer 4 Control Register B15 R/W 0 PRDINT B7 R/W 0 B6 R/W 0 CCLS B5 R/W 0 B4 R/W 0 CKEGS B14 R/W 0 B13 R/W 0 B12 R/W 0 MODE B3 R/W 0 B2 R/W 0 B1 R/W 0 TMRPS B11 R/W 0 B10 R/W 0 B9 R/W 0 Reserved B0 R/W 0 B8 R/W 0 pulse narrower than four sampling clocks will be ignored. The MCP timer 3 and 4 does not support input capture mode. When programmed at counting on both edge, the input clock is halved.
B15-B14
PRDINT
TPR interrupt frequency select
00: Interrupt every period 10: Interrupt once every 4 periods
01: Interrupt once every 2 periods 11: Interrupt once every 8 periods 1x0x: Edge-aligned PWM mode
B13-B10
MODE
Modes select
0xxx: Timer mode 1x1x: Center-aligned PWM mode
B9-B8 B7-B5
Reserved CCLS Counter clear source select 000: TCNT clearing disabled 010: Reserved 100: Reserved 110: Reserved 001: Reserved 011: Reserved 101: Reserved 111: TCNT cleared by P_TMRx_TPR (x = 3, 4) compare match 01: Count at falling edge
B4-B3
CKEGS
Clock edge select
00: Count at rising edge 1X: Count at both edges
B2-B0
TMRPS
Timer pre-scalar select
000: Counts on FCK /1 010: Counts on FCK /16 100: Counts on FCK /256 110: Counts on TCLKA pin input
001: Counts on FCK /4 011: Counts on FCK /64 101: Counts on FCK /1024 111: Counts on TCLKB pin input
5.11.2.6. Timer 3 and 4 Period Register
The P_TMRx_TPR (x = 3, 4) is a 16-bit readable/writable register. It is used to set the period of PWM waveform. When P_TMRx_TCNT (x = 3, 4) register reaches P_TMRx_TPR (x = 3, 4) register value, P_TMRx_TCNT (x = 3, 4) register will be cleared to 0x0000 (up-counting mode) or start down-count (continuous * P_TMR3_TPR (0x7438): Timer 3 Period Register * P_TMR4_TPR (0x7439): Timer 4 Period Register B15 R/W 1 B14 R/W 1 B13 R/W 1 B12 R/W 1 TMRPRD B11 R/W 1 B10 R/W 1 B9 R/W 1 B8 R/W 1 up-/down-counting mode) according to MODE bits programmed in P_TMRx_Ctrl (x = 3, 4) registers. Its default value is 0xFFFF. When P_TMRx_TPR (x = 3, 4) register is set to 0x0000, the P_TMRx_TCNT (x = 3, 4) register counter will stop counting and remain at 0x0000.
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B7 R/W 1
B6 R/W 1
B5 R/W 1
B4 R/W 1 TMRPRD
B3 R/W 1
B2 R/W 1
B1 R/W 1
B0 R/W 1
5.11.2.7. Timer Load-OK Register
In PWM output mode, to prevent partial duty parameters from being loaded incorrectly, correct updating procedures must be followed. The correct updating procedures are first update P_TMR3/4_TGRA-C, then set corresponding LDOK bit to `1'. Once LDOK bit has been set, all duty parameters are considered to be ready, and will be loaded to TGR when counter has been cleared. Then LDOK bit will be cleared to `0' when counter has been cleared. During LDOK be set to `1', the contents of P_TMR3/4_TGRA-C will not be altered by writing to these registers. To correctly set the LDOK bits, the pattern `101010' must be written to P_TMR_LDOK bit 7 to bit 2, otherwise the LDOK bits will not be updated. For example, to set LDOK0 to `1', 0x00A9 must be written to P_TMR_LDOK.
* P_TMR_LDOK (0x740A): Timer Load-OK Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 W 0 B6 W 0 B5 W 0 TLDCHK B15-B8 B7-B2 Reserved TLCKHK Timer load register check bits To change the settings of P_TMR_LDOK, "101010" must be written to these bits. Otherwise LDOK1 and LDOK0 will not be changed. These bits will be read as `0'. B1 LDOK1 P_TMR4_TGRA-C ok to load bit This bit determines whether the values in P_TMR4_TGRA-C are ready to be loaded to PWM module. The values in P_TMR4_TGRA-C will not be loaded to PWM module until this bit has been set to `1'. After the values have been loaded, this bit will be cleared automatically. Note that when this bit has been set, the values in P_TMR4_TGRA-C will not be changed by writing to these registers. B0 LDOK0 P_TMR3_TGRA-C ok to load bit This bit determines whether the values in P_TMR3_TGRA-C are ready to be loaded to PWM module. The values in P_TMR3_TGRA-C will not be loaded to PWM module until this bit has been set to `1'. After the values have been loaded, this bit will be cleared automatically. be changed by writing to these registers. Note that when this bit has been set, the values in P_TMR3_TGRA-C will not B4 W 0 B3 W 0 B2 W 0 B1 W 0 LDOK1 B0 W 0 LDOK0 B11 R 0 B10 R 0 B9 R 0 B8 R 0
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5.11.2.8. Timer 3 and 4 General and Buffer Register
The TGRA, TGRB and TGRC registers are dual function 16-bit readable/writable registers, functioning as compare match registers. The values in TGR and TCNT are constantly compared with each other when the TGR registers are used as compare match registers. When edge-aligned PWM or center-aligned PWM mode is selected, the TGR register controls duty ratio of PWM output. Upon reset, the TGR registers are initialized to 0x0000. The bit TGDIF in P_TMRx_Status (x=3, 4) will be set when TCNT counter value matches the content of P_TMRx_TGRD(x = 3, 4) * P_TMR3_TGRA (0x7448): Timer 3 General Register A * P_TMR3_TGRB (0x7449): Timer 3 General Register B * P_TMR3_TGRC (0x744A): Timer 3 General Register C * P_TMR3_TGRD (0x744B): Timer 3 General Register D * P_TMR4_TGRA (0x744C): Timer 4 General Register A * P_TMR4_TGRB (0x744D): Timer 4 General Register B * P_TMR4_TGRC (0x744E): Timer 4 General Register C * P_TMR4_TGRD (0x744F): Timer4 General Register D B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 TMRGLR B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 TMRGLR * P_TMR3_TBRA (0x7458): Timer 3 Buffer Register A * P_TMR3_TBRB (0x7459): Timer 3 Buffer Register B * P_TMR3_TBRC (0x745A): Timer 3 Buffer Register C * P_TMR4_TBRA (0x745C): Timer 4 Buffer Register A * P_TMR4_TBRB (0x745D): Timer 4 Buffer Register B * P_TMR4_TBRC (0x745E): Timer 4 Buffer Register C B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 TMRBUF B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 TMRBUF B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0 B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0 The timer buffer registers TBRA, TBRB and TBRC are the double buffers of TGRA, TGRB and TGRC, respectively. The value of TGRx (x=A, B, C) can automatically be updated when the period compare match event occurs. That is, the duty ratio value will not be updated until one period ends completely. register and this event could trigger an ADC to start a conversion. Remarkably, the TGRD doest not derive any output waveform.
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5.11.2.9. Timer 3 and 4 Input and Output Control Register
The P_TMRx_IOCtrl (x =3, 4) register controls the action type of PWM compare match output in TIOxA, TIOxB, and TIOxC (x = 3, 4) pins. By setting the CCLS and MODE bits in P_TMRx_Ctrl (x = 3, 4) register will determine the timer action mode. When choosing PWM compare match output mode, the IOAMODE/IOBMODE/IOCMODE bits determines the waveform generation depending on the active clock edge. The MCP 3 and 4 does not have the setting for input capture operation and bits value 1xxx'b of IOAMODE/IOBMODE/IOCMODE are invalid.
* P_TMR3_IOCtrl (0x7413): Timer 3 IO control register * P_TMR4_IOCtrl (0x7414): Timer 4 IO control register B15 R 0 B14 R 0 Reserved B7 R/W 0 B6 R/W 0 IOBMODE B15-B12 Reserved 0000: Initial output 0, 0 output at compare match B11-B8 IOCMODE Select Timer 0/Timer 1 IOC Configuration 0010: Initial output 1, 0 output at compare match 01xx: Output hold 0000: Initial output 0, 0 output at compare match B7-B4 IOBMODE Select Timer 0/Timer 1 IOB Configuration 0010: Initial output 1, 0 output at compare match 01xx: Output hold 0000: Initial output 0, 0 output at compare match B3-B0 IOAMODE Select Timer 0/Timer 1 IOA Configuration 0010: Initial output 1, 0 output at compare match 01xx: Output hold 0001: Initial output 0, 1 output at compare match 0011: Initial output 1, 1 output at compare match 0001: Initial output 0, 1 output at compare match 0011: Initial output 1, 1 output at compare match 0001: Initial output 0, 1 output at compare match 0011: Initial output 1, 1 output at compare match B5 R/W 0 B4 R/W 0 B3 R/W 0 B2 R/W 0 IOAMODE B13 R 0 B12 R 0 B11 R/W 0 B10 R/W 0 IOCMODE B1 R/W 0 B0 R/W 0 B9 R/W 0 B8 R/W 0
5.11.2.10. Timer Start Register
The P_TMR_Start register selects the operation of counter start/stop for the P_TMRx_TCNT (x = 0 ~ 4). When counter operation stopped, its contents will be cleared. Setting TMR3ST or * P_TMR_Start (0x7405): Timer Counter Start Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B11 R 0 B10 R 0 B9 R 0 B8 R 0 TMR4ST bit to 1 would start the P_TMR3_TCNT or P_TMR4_TCNT register immediately and vice versa.
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B7 R 0
B6 R 0 Reserved
B5 R 0
B4 R/W 0 TMR4ST
B3 R/W 0 TMR3ST
B2 R/W 0 TMR2ST
B1 R/W 0 TMR1ST
B0 R/W 0 TMR0ST
B15-B5 B4 B3 B2 B1 B0
Reserved TMR4ST TMR3ST TMR2ST TMR1ST TMR0ST Timer 4 counter start setting Timer 3 counter start setting Timer 2 counter start setting Timer 1 counter start setting Timer 0 counter start setting 0: Counter operation stopped 0: Counter operation stopped 0: Counter operation stopped 0: Counter operation stopped 0: Counter operation stopped 1: Performs counting operation 1: Performs counting operation 1: Performs counting operation 1: Performs counting operation 1: Performs counting operation
* P_TMR3_INT (0x7423): Timer 3 Interrupt Enable Register * P_TMR4_INT (0x7424): Timer 4 Interrupt Enable Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 TADSE B15-8 B7 B6-B5 B4 B3 B2-B0 Reserved TADSE Reserved TPRIE TGDIE Reserved Timer Period Register interrupt enable bit Timer General D Register interrupt enable bit 0: Disable 0: Disable 1: Enable 1: Enable A/D conversion start request by TGRD enable bit 0: Disable 1: Enable B6 R 0 Reserved B5 R 0 B4 R/W 0 TPRIE B3 R/W 0 TGDIE B2 R 0 B1 R 0 Reserved B0 R 0 B11 R 0 B10 R 0 B9 R 0 B8 R 0
Please refer to Timer 3 and 4 Interrupt Status Register.
5.11.2.11. Timer 3 and 4 Interrupt Status Register
The interrupt status register indicates the event generation of period register compare match and compare match of TGRD. These flags show the interrupt sources. An interrupt would be generated when the corresponding interrupt enable bit is set in P_TMRx_INT (x = 3, 4) register. The TCDF represents the counter * P_TMR3_Status (0x7428): Timer 3 Interrupt Status Register * P_TMR4_Status (0x7429): Timer 4 Interrupt Status Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 TCDF B6 R 0 Reserved B5 R 0 B4 R/W 0 TPRIF 104 B3 R/W 0 TGDIF B2 R 0 B1 R 0 Reserved Feb. 16, 2006 Version: 1.1 B0 R 0 B11 R 0 B10 R 0 B9 R 0 B8 R 0 direction when timer is setup to center-aligned PWM mode. The bit TGDIF in P_TMRx_Status (x=3, 4) will be set when timer counter register matches the content of P_TMRx_TGRD(x = 3, 4) register and this event could trigger an ADC to start a conversion.
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B15-8 B7 B6-B5 B4 B3 B2-B0
Reserved TCDF Reserved TPRIF TGDIF Reserved Timer Period Register compare match flag. Timer General D Register compare match flag 0: Compare match not occurred 1: Compare match has occurred 0: Compare match not occurred 1: Compare match has occurred Timer Count direction flag 0: Up-counting 1: Down-counting
: write `1' to clear this flag
5.11.2.12. Timer 3 and 4 Counter Register
The MCP timer 3 and timer 4 have two TCNT counters (P_TMR3_TCNT and P_TMR4_TCNT), one for each channel. The TCNT counters are 16-bit readable registers that increment/decrement according to input clocks. Bits TMRPS in corresponding timer control register can select input clocks. P_TMR3_TCNT and P_TMR4_TCNT increment/decrement in center-aligned PWM mode, while they only increment in other modes. The TCNT counters are initialized to 0x0000 when TCNT value matches the period register. * P_TMR3_TCNT (0x7433): Timer 3 Counter Register * P_TMR4_TCNT (0x7434): Timer 4 Counter Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 TMRCNT B7 R 0 B6 R 0 B5 R 0 B4 R 0 TMRCNT B3 R 0 B2 R 0 B1 R 0 B0 R 0 B11 R 0 B10 R 0 B9 R 0 B8 R 0
5.11.2.13. PWM Output Operation
The MCP timer module has two channels and can perform PWM function up to twelve pins output. The output waveforms have active low at compare match, active high at compare match , forced high and forced low for the corresponding TIOxA, TIOxB, TIOxC, TIOxD, TIOxE and TIOxF (x = 3, 4) output pin using compare match with P_TMRx_TGRA, P_TMRx_TGRB, P_TMRx_TGRC (x = 3, 4) register respectively. Figure 5-59 shows the programming flowchart of PWM operation.
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PWM output operation
[1]
Descriptions: [1.] Program the PWM specified GPIO pins as output port and fault input pin if necessary.
Setup P_IOB_SPE and P_IOC_SPE
[2]
[2.]
Enable the special function of PWM of P_IOB_SPE and P_IOC_SPE.
Enable PWM register write access
[3]
[3.]
Write control word to P_TPWM_Write register to enable the write access.
Setup Timer control register
[4]
[4.]
Setup the CCLS bits to 111'b so that period register determines the period and counter clear source.
Configure IO control and output control register
[5.]
[5]
Select
compare
match
output
mode
through
P_TMRx_IOCtrl (x = 3, 4) register and choose desired PWM waveform through P_TMRx_OutputCtrl (x = 3, 4) register.
Enable period interrupt and start counter
[6]
[6.]
Enable period interrupt and start the counting operation with the bit TMR3ST or TMR4ST is set in P_TMR_Start register.
Figure 5-59 Example programming flowchart of PWM operation
5.11.2.14. Timer Output Enable Register
This register enables/disables the PWM outputs of the specified MCP3 and/or MCP4 timer module. The PWM output will be high-impedance if disabled. Note that this register only takes effect * P_TMR_Output (0x7406): Timer Output Enable Register B15 R 0 Reserved B7 R 0 Reserved B15-B14 B13 B12 B11 B10 B9 B8 B7-B6 B5 B4 Reserved TMR4FOE TMR4EOE TMR4DOE TMR4COE TMR4BOE TMR4AOE Reserved TMR3FOE TMR3EOE Timer 3 IOF Output enable (TIO3F) Timer 3 IOE Output enable (TIO3E) 106 0: Disable 0: Disable 1: Enable 1: Enable Feb. 16, 2006 Version: 1.1 Timer 4 IOF Output enable (TIO4F) Timer 4 IOE Output enable (TIO4E) Timer 4 IOD Output enable (TIO4D) Timer 4 IOC Output enable (TIO4C) Timer 4 IOB Output enable (TIO4B) Timer 4 IOA Output enable (TIO4A) 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable B6 R 0 B14 R 0 B13 R/W 0 TMR4FOE B5 R/W 0 TMR3FOE B12 R/W 0 TMR4EOE B4 R/W 0 TMR3EOE B11 R/W 0 TMR4DOE B3 R/W 0 TMR3DOE B10 R/W 0 TMR4COE B2 R/W 0 TMR3COE B9 R/W 0 TMR4BOE B1 R/W 0 TMR3BOE B8 R/W 0 TMR4AOE B0 R/W 0 TMR3AOE when TIO3A to TIO3F or TIO4A to TIO4F are set to be output pins in special function mode.
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B3 B2 B1 B0
TMR3DOE TMR3COE TMR3BOE TMR3AOE
Timer 3 IOD Output enable (TIO3D) Timer 3 IOC Output enable (TIO3C) Timer 3 IOB Output enable (TIO3B) Timer 3 IOA Output enable (TIO3A)
0: Disable 0: Disable 0: Disable 0: Disable
1: Enable 1: Enable 1: Enable 1: Enable
5.11.2.15. Timer 3 and 4 Output Control Register
The configuration of MCP timer 3 and 4 output control registers is essential to the PWM waveform type used for motor drive applications. The DUTYMODE bit determines which registers used for PWM determines duty ratio. Generally speaking, when driving a BLDC motor with 120 degree PWM mode only P_TMRx_TGRA(x = 3, 4) is the need to setup the duty register. In other words, all of the three P_TMRx_TGRA/P_TMRx_TGRB/P_TMRx_TGRC (x = 3, 4) registers required for 180 degree PWM, including BLDC and ACI motor. The POLP bit determines the PWM active level for IGBT/MOSFET switching device. The UPWM, VPWM and WPWM can be forced H/L or active H/L waveform on specified pin. The bits of POLP, WPWM/VWPM/UPWM and WOC/VOC/UOC make different results in the PWM waveform generation.
PWM Duty is determined by TGRA/TGRB/TGRC, P_TMR4_OutputCtrl .DUTYMODE IOC10/TIO4A/U2 IOC11/TIO4B/V2 IOC12TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOC15/TIO4F/W2N
PWM Duty is determined by TGRA only,
Figure 5-60 PWM output timing with different duty mode selection
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Output high active P_TMR4_OutputCtr .POLP IOC10/TIO4A/U2 IOC11/TIO4B/V2 IOC12TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOC15/TIO4F/W2N
Output low active
Figure 5-61 Output polarity timing
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P_TMR4_OutputCtrl .POLP P_TMR4_OutputCtrl .UPWM P_TMR4_OutputCtrl .VPWM P_TMR4_OutputCtrl .WPWM P_TMR4_OutputCtrl .UOC[1:0] P_TMR4_OutputCtrl .VOC[1:0] P_TMR4_OutputCtrl .WOC[1:0] P_TMR1_Status .TGBIF P_TMR1_Status .PDCIF P_TMR4_Output Ctrl_SYNC[1:0] 1 Output Sync with PDCIF 2 Output Sync with TGBIF 2 3 0 0 2 3 0 0 2 1
2 1
IOC10/TIO4A/U2 IOC11/TIO4B/V2 IOC12TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOC15/TIO4F/W2N
Figure 5-62 PWM Sync mode
* P_TMR3_OutputCtrl (0x7407): Timer 3 Output Control Register * P_TMR4_OutputCtrl (0x7408): Timer 4 Output Control Register B15 R/W 0 DUTYMODE B7 R/W 0 SYNC B14 RW 0 POLP B6 R/W 0 B5 R/W 0 WOC B13 R 0 B12 R 0 Reserved B4 R/W 0 B3 R/W 0 VOC B11 R 0 B10 R/W 0 WPWM B2 R/W 0 B9 R/W 0 VPWM B1 R/W 0 UOC B8 R/W 0 UPWM B0 R/W 0
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B15 B14 B10 B9 B8 B7-B6
DUTYMODE Duty mode select POLP WPWM VPWM UPWM SYNC Phase polarity select W phase PWM output select V phase PWM output select U phase PWM output select UVW phases output synchronization source select
0: U phase in common (same as TGRA 1: Three phases independent register) 0: Active low 0: H/L level output 0: H/L level output 0: H/L level output 00: No sync 1: Active high 1: PWM waveform output 1: PWM waveform output 1: PWM waveform output 01: Synchronized to P_POSx_DectData (x = 0, 1) register change 10: Synchronized to TGRB register compare match of PDCx (x = 0, 1) 11: Synchronized to TGRC register compare match of PDCx (x = 0, 1) WPWM = 0 (H/L output) W phase L L H H H H L L WUN phase L H L H H L H L
B13-B11 Reserved
B5-B4
WOC
W phase output control WOC[1:0] 00 01 10 11 00 01 10 11 W phase CPWM L PWM PWM PWM H CPWM CPWM
POLP=1 (Active high) WPWM = 1 (PWM output) WN phase PWM PWM L CPWM POLP=0 (Active Low) CPWM CPWM H PWM POLP=1 (Active high) VOC[1:0] 00 01 10 11 00 01 10 11 VPWM = 1 (PWM output) V phase CPWM L PWM PWM PWM H CPWM CPWM VN phase PWM PWM L CPWM POLP=0 (Active Low) CPWM CPWM H PWM POLP=1 (Active high) UOC[1:0] 00 01 10 11 00 01 10 11 UPWM = 1 (PWM output) U phase CPWM L PWM PWM PWM H CPWM CPWM UN phase PWM PWM L CPWM POLP=0 (Active Low) CPWM CPWM H PWM H H L L H L H L UPWM = 0 (H/L output) U phase L L H H UN phase L H L H H H L L H L H L VPWM = 0 (H/L output) V phase L L H H VN phase L H L H
B3-B2
VOC
V phase output control
B1-B0
UOC
U phase output control
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5.11.2.16. Timer 3 and 4 Dead Time and Control Register
In complementary PWM mode, each pairs of the complement PWM channel can be used to drive the high side and low side transistors. The PWM signal of each pairs should be totally logic opposite in non-deal case, but actually condition is not. To prevent the active time of PWM signal between low side and high side PWM are overlapping, the dead time unit must be used in complementary PWM mode.
Figure 5-64 Figure 5-63 shows the center-aligned complementary PWM with dead time inserted of timer 3.
Figure 5-64 Active-low PWM mode of dead-time generation
There
are
two
dead-time
timer
control
registers
in
the
output and affected by the setting of POLP bit in the P_TMRx_OutputCtrl (x = 3, 4) register. Three phase dead time feature could be independent enable or disable and the dead time interval is determined through DTP bits at FCK/4 clock source.
SPMC75F2413AP_TMR3_DeadTime and P_TMR4_DeadTime, for MCP channel 3 and channel 4. The dead-time timer only works when programmed in complementary PWM mode. The dead-time timer unit will delay the active edge for positive or lower phase
* P_TMR3_DeadTime (0x7460): Timer 3 Dead Time and Control Register * P_TMR4_DeadTime (0x7461): Timer 4 Dead Time and Control Register B15 R 0 Reserved B14 R/W 0 DTWE B13 RW 0 DTVE B12 R/W 0 DTUE B11 R 0 B10 R 0 Reserved B9 R 0 B8 R 0
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B7 R 0 Reserved B15 B14 B13 B12 B11-B7 B6-B0
B6 R/W 0
B5 R/W 0
B4 R/W 0
B3 R/W 0 DTP
B2 R/W 0
B1 R/W 0
B0 R/W 0
Reserved DTWE DTVE DTUE Reserved DTP Dead-time timer period These bits select the dead-time period. Dead time can be set from 0 to 127 FCK/4 clocks Dead-time timer enable for W phases Dead-time timer enable for V phases Dead-time timer enable for U phases 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable
5.11.2.17. Timer Fault Input Control Register
The fault protection input can be used to establish a must properly select the PWM protection polarity to ensure the safety of the driver circuits of target system. User should aware that the fault input protection only works with complementary PWM mode. Clearing OSF and FTPINIF, releasing fault protection state (PWM high-impedance state) can only be made by a power-on reset or software release procedures. External reset pin reset will not release this fault protection state! high-impedance state for protection by applying an active low state on FTINT1-2 pins summarized in Table 5-19. interrupt will be generated simultaneously. remain in high-impedance state until released. Also, an The PWM outputs will Additionally, the
output compare mode can be activated to compare the complementary PWM output pairs such as U1 and U1N, etc., conducting at the same time. Also note that the OCLS bit in P_Faultx_Ctrl (x = 1, 2) register determines the PWM output compare polarity level; developer Table 5-19 Fault input and PWM output pins combinations Pin Name FTIN1 FTIN2 PWM Output Pairs Combination U1, U1N V1, V1N W1, W1N U2, U2N V2, V2N W2, W2N Pin State Input Input Pin State at fault Input Floating Input Floating Input Floating Input Floating Input Floating Input Floating Description
Input request to set U1, V1, W1, U1N, V1N, W1N output high-impedance Input request to set U2, V2, W2, U2N, V2N, W2N output high-impedance Description All PWM output pins of MCP3 will be set to high-impedance state if these two pins output low/high level, which is determined by P_Fault1_Ctrl.OCLS, simultaneously for more than one clock cycle All PWM output pins of MCP4 will be set to high-impedance state if these two pins output low/high level, which is determined by P_Fault2_Ctrl.OCLS, simultaneously for more than one cycle
The PWM output will be halted (set to high-impedance state) under following circumstances. FTIN1-2 pin input low-level state. The valid FTINT input can be set for holding low for FCK/4 x (1~15).
The complementary PWM output can be set to high-impedance state if upper and lower phase simultaneously output active-level for more than 1 system clock cycle. PLL or oscillator stopped Fast Interrupt Request (FIQ) will be generated.
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IOC9/FTIN2 Write "55AAh" then "AA55h" to P_Fault2_Release will clear P_Fault2_Ctrl.FTPINIF and disable P_Fault2_Ctrl.FTPINE
Fault protection sampling time P_Fault2_Ctrl .FTPINE P_Fault2_Ctrl .FTPINIF
All outputs turn to Hi-Z state IOC10/TIO4A/U2 IOC11/TIO4B/V2 IOC12TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOC15/TIO4F/W2N
Figure 5-65 Fault error timing
P_Fault2_Ctrl.OCE Write "AA55h" then "55AAh" to P_Fault2_Release will clear P_Fault2_Ctrl.OSF and disable P_Fault2_Ctrl.OCE P_Fault2_Ctrl.OSF Output Compare Error occurs IOC10/TIO4A/U2 IOC11/TIO4B/V2 IOC12TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOC15/TIO4F/W2N
Figure 5-66 Output compare error
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External reset Power-on reset Crystal oscillator System clock P_Clk_Ctrl.OSCSF Write P_Clk_Ctrl.OSCSF=1 to clear this flag OSC fail OSC fail =1 make MCP3 and MCP4 output as Hi-Z All outputs turn to Hi-Z state IOC10/TIO4A/U2 IOC11/TIO4B/V2 IOC12TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOC15/TIO4F/W2N Start PWM output Only power-on reset can clear PMC OSC Fail latch
Figure 5-67 Oscillator stopped timing
* P_Fault1_Ctrl (0x7466): Fault input 1 Control and Status Register * P_Fault2_Ctrl (0x7467): Fault input 2 Control and Status Register B15 R/W 0 OCE B7 R/W 0 FTPINE B15 B14 B13 B12 B11-B8 OCE OCIE OCLS OSF B14 RW 0 OCIE B6 R/W 0 FTPINIE B13 R/W 0 OCLS B5 R/W 0 FTPINIF Output compare enable Output compare interrupt enable Output compare polarity level select Output short flag B12 R/W 0 OSF B4 R 0 Reserved 0: Disable 0: Disable 0: Compare low-level B3 R/W 0 B2 R/W 0 FTCNT 1: Enable 1: Enable 1: Compare high-level B11 R 0 B10 R 0 Reserved B1 R/W 0 B0 R/W 0 B9 R 0 B8 R 0
Software needs to set the OCE bit to `1' again to active the output short protection function after this flag is cleared.
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B7 B6 B5 B4 B3-B0
FTPINE FTPINIE FTPINIF Reserved FTCNT
Fault input pin 1/2 enable Fault input 1/2 interrupt enable Fault input 1/2 status flag
0: Disable 0: Disable 0: Not occurred
1: Enable 1: Enable 1: Occurred
Fault protection sampling time
FCK/4 * n, n = 1 to 15. User should note that setting the FTCNT value to 0 will always make the external fault input interrupt happen even the FTIN1/2 pin is at logic high state. If FTPINIE bit is set, FTPINIF will not be able to be cleared and the interrupt routine executed recursively due to incorrect FTCNT setting. This will cause the system unpredictable.
: : :
write `1' to clear this flag write "0xAA55" then "0x55AA" to P_Faultx_Release (x = 1, 2) will clear this flag and also disable output compare. write "0x55AA" then "0xAA55" to P_Faultx_Release (x = 1, 2) will clear this flag and also disable fault input pin.
5.11.2.18. Timer Fault Release Register
To release the PWM output high-impedance state caused by fault input, first check the asserted fault pin input flag FTPINIF in P_Faultx_Ctrl (x = 1, 2) register, then write "0x55AA" and "0xAA55" sequentially to its corresponding fault release To release the PWM high-impedance state caused because oscillator fail, first clear oscillator fail flag OSCSF in P_Clk_Ctrl To release the PWM output high-impedance state from PWM output short-circuit logic detection presents inside the chip, first register, then write "0x5555" and "0xAAAA" sequentially to its corresponding fault release P_Faultx_Release (x = 1, 2) register. P_Faultx_Release (x = 1, 2) register. check output short flag OSF in P_Faultx_Ctrl (x = 1, 2) register, then write "0xAA55" and "0x55AA" sequentially to its corresponding fault release P_Faultx_Release (x = 1, 2) register.
* P_Fault1_Release(0x746A): Fault 1 Flag Release Register * P_Fault2_Release(0x746B): Fault 2 Flag Release Register B15 W 0 B14 W 0 B13 W 0 B12 W 0 FTRR B7 W 0 B6 W 0 B5 W 0 B4 W 0 FTRR B15-B0 FTRR FTRR: Fault release control words B3 W 0 B2 W 0 B1 W 0 B0 W 0 B11 W 0 B10 W 0 B9 W 0 B8 W 0
5.11.2.19. Timer Overload Protection Control and Status Register
The SPMC75F2413A devices contain an overload protection circuit. The circuit starts operating when the overload protection The overload protection input is sampled Sampling number can be set from 0 to 15 times. input (OL) is pulled low. by clock FCK/4. The output disabled phases during overload protection are to disable no phases, all phases, PWM phases, or all upper/all lower phases. When to disable all upper or all lower phases is selected (P_OLx_Ctrl.OLMD = 3, x = 1, 2), motor drive PWM output is determined by their turn-on status immediately before being disabled. When two or more upper phases are active, all upper phases are turned on and all lower phases are turned off; when two or more lower phases are active, all upper phases are turned off and all lower phases are turned on. (c) Sunplus Innovation Technology Inc. Proprietary & Confidential 115 Table 5-20 and Table Feb. 16, 2006 Version: 1.1
There are three methods to deactivate overload protection: deactivate by a timer, deactivate by PWM synchronous, or deactivate manually. These methods can be used when the overload protection input has been released back to high.
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5-21 show the overload function behavior depending on POLP bit in P_TMRx_OutputCtrl (x = 3, 4) register and OLMD bit when such
condition happened. To disable a phase means to put the phase in inactive level.
IOC8/OL2 Overload protection sampling time P_OL2_Ctrl .OLST Release from overload protection state immediately when OL2 pin returned to high level. P_OL2_Ctrl .RTOL
Write P_OL2_Ctrl.OLIF = 1 to clear this flag
P_OL2_Ctrl .OLIF P_TMR3_TCNT[15:0] 2D Counter stop counting if P_OL2_Ctrl.CNTSP = 1 and P_OL2_Ctrl.OLMD 0 P_OL2_Ctrl .CNTSP P_OL2_Ctrl .OLMD[1:0] IOC10/TIO4A/U2 U2 and W2 are H/L output IOC11/TIO4B/V2 IOC12TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOC15/TIO4F/W2N U2N and W2N are H/L output Turn off respective PWM output if P_OL2_Ctrl.OLMD = 2 2
Figure 5-68 Stop PWM output only when overload occurs
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IOC8/OL2 Overload protection sampling time P_OL2_Ctrl .OLST Release from overload protection state after delaying one PWM period cycle when OL2 pin returned to high level P_TMR4_Status .TPRIF P_OL2_Ctrl .RTPWM Write P_OL2_Ctrl.OLIF = 1 to clear this flag P_OL2_Ctrl .OLIF P_TMR4_TCNT[15:0] Counter continues counting if P_OL2_Ctrl.CNTSP = 0 P_OL2_Ctrl .CNTSP P_OL2_Ctrl .OLMD[1:0] IOC10/TIO4A/U2 Turn off all output if P_OL2_Ctrl.OLMD = 1 1
IOC11/TIO4B/V2 IOC12TIO4C/W2 IOC13/TIO4D/U2N IOC14/TIO4E/V2N IOC15/TIO4F/W2N
Figure 5-69 Stop all output when overload occurs
Table 5-20 Overload protection interrupt when POLP = 1 POLP = 1 OLMD 0 0 1 1 0 1 0 1 TIOxA ~ TIOxF Phase Output State (x = 3, 4) No phases disabled All phases disabled PWM/CPWM phases disabled. (Refer to P_TMRx_OutputCtrl) (1) Any upper two phases are detected as high level, and then disable all lower phases. 117 Issue overload protection interrupt when any upper two phases or lower two phases are detected as high level, Feb. 16, 2006 Version: 1.1 Overload Protection Interrupt Capability No Yes Yes
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POLP = 1 OLMD
TIOxA ~ TIOxF Phase Output State (x = 3, 4) (2) Any lower two phases are detected as high level, and then disable all upper phases. If either condition (1) or (2) is not satisfied, no phases are disabled.
Overload Protection Interrupt Capability otherwise no interrupt is issued.
Table 5-21 Overload protection interrupt when POLP = 0 POLP = 1 OLMD 0 0 1 0 1 0 TIOxA ~ TIOxF Phase Output State (x = 3, 4) No phases disabled All phases disabled PWM/CPWM phases disabled. (Refer to P_TMRx_OutputCtrl) (1) Any upper two phases are detected as low level, and then disable all lower phases. 1 1 (2) Any lower two phases are detected as low level, and then disable all upper phases. If either condition (1) or (2) is not satisfied, no phases are disabled. * P_OL1_Ctrl(0x7468): Overload Input 1 Control and Status Register * P_OL2_Ctrl(0x7469): Overload input 2 Control and Status Register B15 R/W 0 OLEN B7 R 0 OLIE B14 RW 0 CNTSP B6 R 0 OLIF B5 R 0 Reserved B13 R/W 0 OLMD B4 R 0 B12 R/W 0 B11 R/W 0 OLST B3 R/W 0 B10 R/W 0 RTTMB B2 R/W 0 OLCNT B9 R/W 0 RTPWM B1 R/W 0 B8 R/W 0 RTOL B0 R/W 0 Issue overload protection interrupt when Any upper two phase are detected as low level, otherwise no interrupt is issued. Overload Protection Interrupt Capability No Yes Yes
B15 B14
OLEN CNTSP
Overload protection enable Stop PWM counter (P_TMR3_TCNT/P_TMR4_TCNT) during overload protection occurring
0: Disable 0: Do not stop
1: Enable 1: Stop the counter
B13-B12
OLMD
Output disabled phases during overload protection occurring
00: No phases disabled 10: PWM phases disabled
01: All phases disabled, i.e. on turn-off state 11: All upper or all lower phases are disabled depending on the active phases
B11 B10
OLST RTTMB
Overload protection status Release from TGRB selection
0: No operation 0: keep overload protection
1: Under protection 1: Release from overload protection after P_TMRx_TGRB (x = 0, 1) register compare match occurred when OLx (x = 1, 2) pin returned to high level.
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B9
RTPWM
Release from PWM selection
0: keep overload protection
1:
Release
from
overload
protection state after delaying one PWM period cycle when OLx (x = 1, 2) pin returned to high level. B8 RTOL Release from OL pin selection 0: keep overload protection 1: Release from overload protection state immediately when OLx (x = 1, 2) pin returned to high level. B7 B6 B5-B4 B3-B0 OLIE OLIF Reserved OLCNT Overload protection sampling time. FCK/4 * n, n = 1 to 15. User should note that setting the OLCNT value to 0 will always make the external fault input interrupt happen even the OL1/2 pin is at logic high state. If OLIE bit is set, OLIF will not be able to be cleared and the interrupt routine executed recursively due to incorrect OLCNT setting. This will cause the system unpredictable.
: write `1' to clear this flag
Overload interrupt enable bit Overload interrupt flag
0: Disable 0: Not occurred
1: Enable 1: Has occurred
5.12. Compare Match Timer
The device has a compare match timer (CMT) comprising two 16-bit timer channels. Each channel has a 16-bit up-count The clock counter and can generate interrupt at set intervals. will be set if the register value of P_CMTx_TCONT (x=0, 1) matches that of P_CMTx_TPR (x=0, 1), respectively. The counters will start counting when STx (x=0, 1) in P_CMT_Start is set, independently.
input source can be selected from FCK/1, FCK/2, FCK/4, FCK/8, FCK/16, FCK/64, FCK/256, or FCK/1024. The compare match interrupt
P_CMT_Start .ST0 Write P_CMT_Start.ST0 = 1 to start counting P_CMT_Ctrl.CKA[2:0] 2 Write P_CMT_Ctrl.CKA to select counter clock. Counter0 clock
6000
1
P_CMT0_TCNT[15:0] P_CMT_TPR[15:0]
0
1 2 3 4 5 6 7 8 9 10 111213 14 6000
0 1 2 3 4 5 6 7 8 9 10 1112 6000 Set after one system clock
Write P_CMT0_TPR to configure period P_CMT_Ctrl.CM0IF
Write P_CMT_Ctrl.CM0IF = 1 to clear this flag
Figure 5-70 CMT timing
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* P_CMT_Start (0x7500)Compare Match Timer Start Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R 0 B6 R 0 B5 R 0 Reserved B15-B2 B1 B0 Reserved ST1 ST0 Compare match timer 0: 1 counter start 0 counter start Compare match timer 0: P_CMT1_TCNT P_CMT0_TCNT counter counter operation 1: operation 1: P_CMT1_TCNT P_CMT0_TCNT counter counter operation operation stopped, and cleared to 0x0000 stopped, and cleared to 0x0000 enabled enabled B4 R 0 B3 R 0 B2 R 0 B1 R/W 0 ST1 B0 R/W 0 ST0 B11 R 0 B10 R 0 B9 R 0 B8 R 0
* P_CMT_Ctrl (0x7501)Compare Match Timer Control and Status Register B15 R/W 0 CM1IF B7 R/W 0 CM0IF B15 B14 CM1IF CM1IE B14 R/W 0 CM1IE B6 R/W 0 CM0IE B5 R 0 B13 R 0 B12 R 0 Reserved B4 R 0 Reserved 0: Not matched disable B3 R 0 B2 R/W 0 B11 R 0 B10 R/W 0 B9 R/W 0 CKB B1 R/W 0 CKA 1: Matched enable B0 R/W 0 B8 R/W 0
CMT1 compare match interrupt flag CMT1 enable compare match
interrupt 0: CMT1 compare match interrupt 1: CMT1 compare match interrupt
B13-B11 Reserved B10-B8 CKB CMT1 clock select bits 000: FCK / 1 010: FCK / 4 100: FCK / 16 110: FCK / 256 B7 B6 B5-B3 B10-B8 CM0IF CM0IE Reserved CKA CMT0 clock select bits 000: FCK / 1 010: FCK / 4 100: FCK / 16 110: FCK / 256
: write `1' to clear this flag
001: FCK / 2 011: FCK / 8 101: FCK / 64 111: FCK / 1024 1: Matched enable
CMT0 compare match interrupt flag CMT0 enable compare match
0: Not matched disable
interrupt 0: CMT0 compare match interrupt 1: CMT0 compare match interrupt
001: FCK / 2 011: FCK / 8 101: FCK / 64 111: FCK / 1024
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* P_CMT0_TCNT (0x7508)Compare Match Timer 0 Counter Register * P_CMT1_TCNT (0x7509)Compare Match Timer 1 Counter Register Compare match timer counter is a 16-bit register used as an up-counter. B15 R 0 B14 R 0 B13 R 0 B12 R 0 CMTCNT B7 R 0 B6 R 0 B5 R 0 B4 R 0 CMTCNT * P_CMT0_TPR (0x7510)Compare Match Timer 0 Period Register * P_CMT1_TPR (0x7511)Compare Match Timer 1 Period Register The compare match timer period register is a 16-bit register used to set the period for compare match function. The initial value is B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 CMTPR B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 CMTPR B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 0x0000. The P_CMTx_TCNT (x = 0, 1) will be cleared to 0x0000 when a new value has been written to P_CMTx_TPR (x = 0, 1). B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0 B3 R 0 B2 R 0 B1 R 0 B0 R 0 The initial value is 0x0000. B11 R 0 B10 R 0 B9 R 0 B8 R 0
5.13. Time Base Module
The Time Base Module is used to produce the reference clock needed by other modules on the chip. It comprises a 16-bit ripple counter, can generate reference clocks from FCK/2, FCK/4 ~ FCK/1024 ~ FCK/65536. Only the clocks of FCK/2, FCK/4 ~ FCK/1024 supply the peripherals of SPMC75F2413A chip. Time base counter can be cleared by writing 0x5555 to Time Base Reset Register (P_TMB_Reset). The peripherals using the clock source provided by the time base module will be a concern if user intends to clear time base. By using the divider of the Time Base Module, a 50% duty cycle pulse can be produced to drive a buzzer device. time base clock is sent to pin IOC4/BZO. The selected
Reset strobe Write P_TMB_Reset=0x5555 to reset timebase counter TimeBase Counter[15:0] P_BZO_Ctrl.BZOCK 3 Write P_BZO_Ctrl.BZOCK=3 to select Buzzer output frequency as FCK/2048 IOC4/BZO 0
Figure 5-71 Timebase and buzzer output timing
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* P_TMB_Reset (0x70B8)Time Base Reset Register Write 0x5555 to this register to reset the time base counter register to initial the clock sources of all peripherals on the chip. B15 W 0 B14 W 0 B13 W 0 B12 W 0 TBRR B7 W 0 B6 W 0 B5 W 0 B4 W 0 TBRR * P_BZO_Ctrl (0x70B9) Buzzer Output Control Register B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 CMTPR B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 CMTPR B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0 B3 W 0 B2 W 0 B1 W 0 B0 W 0 B11 W 0 B10 W 0 B9 W 0 B8 W 0
B15 B14-B2 B1-B0
BZOEN Reserved BZOCK
Buzzer output enable select bit
0: Disable
1: Enable
Buzzer output frequency select bits
00: FCK / 16384 10: FCK / 4096
01: FCK / 8192 11: FCK / 2048
5.14. Serial Communication Interface
The SPMC75F2413A supports two serial communication interfaces: SPI (Standard Peripheral Interface) and UART (Universal Asynchronous Receiver/Transceiver).
Three external pins: - SCK: clock input/output pin (shared with IOB11) - SDO: data output pin (shared with IOB13) - SDI: data input pin (shared with IOB12) Supports full-duplex synchronous transfer Two operation modes: master and slave Baud rate: 6 programmable transfer rate / Max. 6Mbps at 24MHz CPU clock Data word length: 8-bit Programmable clock phase and clock polarity settings Selectable data strobe time: input data bit sampled at the middle/end of data output time Three selectable sampling clock sources for noise immunity The function diagram of SPI module is as follows.
5.14.1. SPI (Standard Peripheral Interface)
The SPMC75F2413A devices include the three-pin SPI module. The SPI is a high-speed synchronous serial I/O that allows a serial of bit stream to be transmitted out or received into the device at a programmable transfer rate. The SPI supports full-duplex synchronous transfer between a master device and a slave device. The SPMC75F2413A supports both master and slave modes. The parameters such as operation mode, clock frequency, clock phase, and clock polarity are user programmable. module provides the following features: The SPI
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Figure 5-72 Function block diagram of SPI interface
5.14.2. SPI Operation 5.14.2.1. SPI Master Mode
As in master mode, the shifting clock (SPICLK) is generated by SPI module. There are two control bits to control the clock phase (SPIPHA) and polarity (SPIPOL) in the P_SPI_Ctrl register. The transmission starts immediately from data is written to the P_SPI_TxBuf register. In contrast, while SPI interface is received one byte successfully, After software writes one byte through P_SPI_TxBuf register, the data is latched into its internal transmission buffer. If the shift register is not shifting data, the data will be loaded to the shift register and start transmitting at the next SCLK phase. On the other hand, if the shift register is busy in shifting data (SPITXBF flag is set in P_SPI_TxStatus register), the new data will not be shifted out until the present byte has been shifted out. The SPI shifts the data from MSB to LSB through the SPIDO pin. The 8-bit data is shifted out after eight SCLK cycles. At the same The following diagram depicts the timing scheme on SPI master mode for different operation types (polarity control bit equals "1" or "0", phase control bit equals "1" or "0", and sample strobe control bit equals "1" or "0"). the received data will be latched into reception buffer. At that time, SPIRXIF bit in P_SPI_RxStatus register will be set and a SPI interrupt will be issued to CPU if the SPIRXIE bit in the P_SPI_RxStatus register is set. time, the data is also shifted in through SDI pin. When each 8-bit transfer is completed, the SPITXIF bit in P_SPI_TxStatus register will be set; besides, a SPI interrupt will be generated if the SPITXIE bit is set to `1' in P_SPI_TxStatus register.
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BUS write to P_SPI_TxBuf SCK(SCKPHA=0, SCKPOL=0) SCK(SCKPHA=0, SCKPOL=1) SCK(SCKPHA=1, SCKPOL=0) SCK(SCKPHA=1, SCKPOL=1) SDO SDI (SCKPHA=0) SDI (SCKPHA=1) Sample Strobe (SPISMPS=0) Sample Strobe (SPISMPS=1)
Figure 5-73 SPI mode timing, Master Mode
D7 D7 D7
D6 D6 D6
D5 D5 D5
D4 D4 D4
D3 D3 D3
D2 D2 D2
D1 D1 D1
D0 D0 D0
5.14.2.2. SPI Slave Mode
In slave mode, the shifting clock SCLK comes from external SPI master, so the transmission starts from the first external SCLK event. To transmit, the firmware should write the data to its transmitting buffer before the first SCK comes from the master. Both master and slave devices must be programmed with the same SCLK phase and polarity for transmitting and receiving data. If the clock phase bit (SPIPHA) is "1", the first data bit to be shifted out starts right after the command written to P_SPI_TxBUF register. If the clock phase bit (SPIPHA) is "0", the first data bit to be shifted will start after first SCLK edge.
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Write data to P_SPI_TxBuf SCK(SCKPOL=0 SPIHA=0) SCK(SCKPOL=1 SPIHA=0) SCK(SCKPOL=0 SPIHA=1) SCK(SCKPOL=1 SPIHA=1) SDO SDI Sample strobe IRQ flag SSB D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0
Figure 5-74 SPI mode timing, Slave Mode, SPIPHA = 0
* P_SPI_Ctrl (0x7140): SPI Control Register B15 R/W 0 SPIE B7 R 0 Reserved B15 B14-B12 B11 B10-B9 SPIE Reserved SPIRST SPISPCLK Write 1 to reset. It only generate one pulse to reset the SPI module except for the register setting Sampling clock select bits 00: no sampling 10: FCK/2 B8 B7-B6 B5 B4 B3 B2-B0 SPIMS Reserved SPIPHA SPIPOL SPISMPS SPIFS SPI clock phase. SPI clock phase select, see SPI Master Mode Timing SPI clock polarity. SPI clock polarity select, see SPI Master Mode Timing SPI sample mode selection for master mode Master mode clock frequency selection 0: input data bit sampled at the 1: input data bit sampled at the middle of data output time 000: FCK/4 010: FCK/16 100: FCK/64 end of data output time 001: FCK/8 011: FCK/32 1xx: FCK/128 SPI mode selection 0: Master mode 01: FCK 11: FCK/4 1: Slave mode SPI enable B6 R 0 B14 R 0 B13 R 0 Reserved B5 R/W 0 SPIPHA B4 R/W 0 SPIPOL B12 R 0 B11 W 0 SPIRST B3 R/W 0 SPISMPS 0: Disable B2 R/W 0 B10 R/W 0 SPISPCLK B1 R/W 0 SPIFS 1: Enable B9 R/W 0 B8 R/W 0 SPIMS B0 R/W 0
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* P_SPI_TxStatus (0x7141): SPI Transmit Status Register The SPITXBF will be set when P_SPI_TxBUF is written and be cleared immediately when the session of SPI transmission starts. B15 R/W 0 SPITXIF B7 R 0 B14 R/W 0 SPITXIE B6 R 0 B13 R/W 0 SPITXBF B5 R 0 B4 R 0 Reserved B15 B14 B13
:
B12 R 0
B11 R 0
B10 R 0 Reserved
B9 R 0
B8 R 0
B3 R 0
B2 R 0
B1 R 0
B0 R 0
SPITXIF SPITXIE SPITXBF
SPI Transmit interrupt flag SPI Transmit interrupt enable Transmission buffer full flag
0: Not occur 0: Disable 1: Transmission buffer full
1: Happened, write 1 to clear 1: Enable 0: Transmission buffer is empty
B12-B0 Reserved write `1' to clear this flag
* P_SPI_TxBuf (0x7142): SPI Transmission Buffer Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 SPITXBUF B15-B8 B7-B0 Reserved SPITXBUF Write data sends to SPIDO pin B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R 0 B10 R 0 B9 R 0 B8 R 0
* P_SPI_RxStatus (0x7143): SPI Receive Status Register The FERR will be set when reception buffer receives the new data before reading the former out. It will be cleared immediately when reading P_SPI_RxBuf. B15 R/W 0 SPIRXIF B7 R 0 B14 R/W 0 SPIRXIE B6 R 0 B5 R 0 B13 R 0 B12 R 0 Reserved B4 R 0 Reserved B15 B14 B13-B11 B10
:
B11 R 0
B10 R/W 0 FERR
B9 R 0 Reserved B1 R 0
B8 R 0
B3 R 0
B2 R 0
B0 R 0
SPIRXIF SPIRXIE Reserved FERR
SPI receive interrupt flag SPI receive interrupt enable
0: Not occur 0: Disable
1: Happened, write 1 to clear 1: Enable
Buffer full and overwrite error bit
0: No overwrite error occurs
1: overwrite error happened
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* P_SPI_RxBuf (0x7144): SPI Reception Buffer Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 SPIRXBUF B15-B8 B7-B0 Reserved SPIRXBUF Read data from SPIDI pin B3 R/W 0 B2 R/W 0 B1 R/W 0 B0 R/W 0 B11 R 0 B10 R 0 B9 R 0 B8 R 0
5.14.3. UART (Universal Asynchronous Receiver/Transceiver)
The UART module built in SPMC75F2413A performs serial-to-parallel conversion on data received from an external device and it performs parallel-to-serial conversion on data transmitted to the external device. following features: Four external pins: - RXD1: data reception pin 1 (shared with IOB12) - TXD1: data transmission pin 1 (shared with IOB13) - RXD2: data reception pin 2 (shared with IOC0) - TXD2: data transmission pin 2 (shared with IOC1) Provides standard asynchronous, full-duplex communication Programmable trans-receive baud rate Parity can be even, odd or disabled for generation and detection Stop bit width can be 1 or 2 bits Support transmitting interrupt Support receiving interrupt High noise rejection for bit receiving (majority decision of 3 consecutive samples in the middle of received bit time) Framing and Parity error detection during reception Overrun detection Programmable baud rate from 300 bps to 115200 bps Support Transmission/Reception data channel selection This module provides the
5.14.4. UART Operation
There exists a baud rate register and a 16-bit timer to generate the baud rate. Each times the timer increments from its maximum The clock The count (0xFFFF), a clock is sent to the baud rate circuit.
is through divid-by-16 counter to generate the baud rate. timer is reloaded automatically the value in baud rate register.
Baud Rate = FCK / [ 16 x (65536 - P_UART_BaudRate)] The content in baud rate register is taken as a 16-bit unsigned number. To derive the required baud rate register values from a known baud rate, use the equation and refer to Table 5-22: P_UART_BaudRate = 65536 - FCK / (16 x Baud Rate) Table 5-22 P_UART_BaudRate setup value at FCK = 24.0 MHz Baud Rate 115200 bps 57600 bps 19200 bps 9600 bps 4800 bps 2400 bps 1200 bps 600 bps 300 bps Baud Rate Timer Reload Register Value @ 24MHz 0xFFF3 0xFFE6 0xFFB2 0xFF64 0xFEC8 0xFD8F 0xFB1E 0xF63C 0xEC78
The UART begins transmitting after the first rollover of the divide-by-16 counter after the software writes to the P_UART_Data register. The UART transmits data on the TXD2/TXD1 pin in the following order: start bit, 8 data bits (LSB first), parity bit (Parity Enable mode only), stop bit. The TXIF bit in P_UART_Status register is set after 2 FCK cycles when the stop bit is transmitted. The TXIF bit is cleared automatically after the software writes to the P_UART_Data register. Figure 5-77 shows the data transmission timing.
between TXD1/RXD1 and TXD2/RXD2. Any one of the transmission channels can cooperate with one of reception channels. Figure 5-75 and Figure 5-76 shows the block diagram and the data format for UART, respectively.
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Figure 5-75 UART block diagram
Figure 5-76 UART Data Format
Figure 5-77 Data Transmission Timing
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Reception begins at the falling edge of a start bit received on RXD2/RXD1 pin, when enabled by the RXEN bit in P_UART_Ctrl register. For this purpose, RXD2/RXD1is sampled 16 times per bit for any baud rate. When a falling edge of a start bit is detected, the divide-by-16 counter used to generate the receiving clock is reset to align the counter rollover to the bit boundaries. For noise rejection, the serial port establishes the content of each received bit by a majority decision of 3 consecutive samples in the middle of each bit time. This is especially true for the start bit. If the falling edge on RXD2/RXD1is not verified by a majority decision of 3 consecutive samples logic low level, then the serial port stops reception and waits for another falling edge on RXD2/RXD1. Figure 5-78 shows the data sampling scheme. After receiving the stop bit, the UART module writes the received byte to the P_UART_Data register and set the RXIF and RXBF bit. The serial port then waits for another high-to-low transition on the RXD1/ RXD2 pin. Figure 5-79 shows the data reception timing.
If the received byte is not read out before the next reception finished, the data will be over-written by the new received. In every reception session, RXBF is checked after receiving the stop bit. If the RXBF bit is set, the OE will be set to record this overrun error event. Remarkably, the OE will be cleared automatically if the error check success in the following session. Figure 5-80 shows the overrun error timing.
The parity and frame check is used for improving the reliability of reception. The parity can be even or odd according to the configuration of P_UART_Ctrl.PSEL. The parity check is performed after receiving parity bit if P_UART_Ctrl.PEN is enabled. The PE bit will be set if any parity error. Please refer to Figure 5-81 for timing diagram. The Stop Bit is the part of the UART data formation. If the reception session fails to receive Stop Bit, the integrity of the data frame is lost. The FE bit is set to record this frame error event. Figure 5-82 shows the frame error timing. Remarkably, PE and FE will be clear automatically if the error checks success in the following session, respectively.
0 Baudrate clock RXD1/RXD2
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9 10
Start bit
Sampled three times
D0
Figure 5-78 Data sampling scheme
IOC0/RXD2 Shift register P_UART_Data .UARTDATA P_UART_Status. RXIF xxxxxxx--
Last bit xxxxxxxx-
Stop bit 1xxxxxxxx xxxxxxxx
Read P_UART_Data to clear this flag
Figure 5-79 RX buffer full
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IOC0/RXD2 Shift register P_UART_Data .UARTDATA P_UART_Data .OE P_UART_Status. RXBF xxxxxxx--
Last bit xxxxxxxxyyyyyyyy
Stop 1xxxxxxxx xxxxxxxx
Figure 5-80 Overrun error timing
IOC0/RXD2 Shift register P_UART_Data .PE
D7 xxxxxxxx--
Parity pxxxxxxxx-
Stop 1pxxxxxxxx
Figure 5-81 Parity Error timing
IOC0/RXD2 Shift register P_UART_Data .FE XXXXXXX--
Last bit XXXXXXXX-
Stop bit 0XXXXXXXX
Figure 5-82 Frame Error timing
* P_UART_Data (0x7100): UART Data Register B15 R 0 B14 R 0 Reserved B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 UARTDATA B15-B12 B11 B10 B9 B8 B7-B0
Note:
B13 R 0
B12 R 0
B11 R 0 OE B3 R/W 0
B10 R 0 Reserved B2 R/W 0
B9 R 0 FE B1 R/W 0
B8 R 0 PE B0 R/W 0
Reserved OE Reserved PE FE UARTDATA Parity Error (Ready-only) Frame Error (Ready-only) UART Data Read/Write Register 0: Not Occurred 0: Not Occurred 1: Occurred 1: Occurred Overrun Error (Ready-only) 0: Not Occurred 1: Occurred
Read-only error flags in bit [11:8] have the same function with control register bits located in bit[3:0] of P_UART_RXStatus register.
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* P_UART_RXStatus (0x7101): UART Reception Error Flag Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 B6 R/W 0 Reserved B15-B4 B3 B2 B1 B0 Reserved OE Reserved FE PE Parity Error Frame Error Read 0: Not Occurred Read 0: Not Occurred Read 1: Occurred Read 1: Occurred Overrun Error Read 0: Not Occurred Read 1: Occurred B5 R/W 0 B4 R/W 0 B3 R/W 0 OE Bb2 R 0 Reserved B1 R/W 0 FE B0 R/W 0 PE B11 R 0 B10 R 0 B9 R 0 B8 R 0
* P_UART_Ctrl (0x7102): UART Control Register B15 R/W 0 RXIE B7 R 0 B14 R/W 0 TXIE B6 R 0 Reserved B15 B14 B13 B12 B11 B10 B9 B8-B4 B3 B2 B1 B0 RXIE TXIE RXEN TXEN Reset TXCHSEL RXCHSEL Reserved SBSEL PSEL PEN Reserved Stop Bit Size Selection. Parity Selection Parity Enable 0: 1 Stop Bit 0: Odd Parity (if PEN= 1) 0: Disabled 1: 2 Stop Bit 1: Even Parity (if PEN= 1) 1: Enabled Receive Interrupt Enable Transmit Interrupt Enable UART reception enable UART transmission enable Software reset Transmission data channel selection Reception data channel selection 0: UART transmission to TXD2 on 1: UART transmission to TXD1 on IOC1 pin IOC0 pin IOB12 pin IOB13 pin 0: UART reception from RXD2 on 1: UART reception from RXD1 on B13 R 0 RXEN B5 R 0 B12 R/W 0 TXEN B4 R 0 B11 W 0 Reset B3 R/W 0 SBSEL 0: Disabled 0: Disabled 0: Disabled 0: Disabled B10 R/W 0 TXCHSEL B2 R/W 0 PSEL B9 R/W 0 RXCHSEL B1 R/W 0 PEN 1: Enabled 1: Enabled 1: Enabled 1: Enabled B8 R 0 Reserved B0 R 0 Reserved
* P_UART_BaudRate(0x7103): UART Baud Rate Setup Register B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 UARTBUD B11 R/W 0 B10 R/W 0 B9 R/W 0 B8 R/W 0
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B7 R/W 0
B6 R/W 0
B5 R/W 0
B4 R/W 0 UARTBUD
B3 R/W 0
B2 R/W 0
B1 R/W 0
B0 R/W 0
B15-B0
UARTBUD
UART Baud Rate Divisor
Baud Rate = CPUCLK / [ 16 x (65536 - P_UART_BaudRate)] The value of P_UART_BaudRate register is calculated as follows P_UART_BaudRate = 65536 - CPUCLK / (16 x Baud Rate)
* P_UART_Status (0x7104): UART Status Register B15 R 0 RXIF B7 R 0 Reserved B15 B14 B13-B7 B6 B5-B4 B3 B2-B0 RXIF TXIF Reserved RXBF Reserved BY Reserved Transmitting busy flag. 0: transmitter is ready 1: Transmitter is busy Receiving buffer full flag 0: reception buffer is not full 1: Reception buffer is full B14 R 1 TXIF B6 R 0 RXBF Receive Interrupt Flag Transmit Interrupt Flag B5 R 0 Reserved B4 R 0 B3 R 0 BY B13 R 0 B12 R 0 B11 R 0 Reserved B2 R 0 B1 R 0 Reserved B0 R 0 B10 R 0 B9 R 0 B8 R 0
1: a valid byte received complete, an interrupt is 0: no reception interrupt asserted if RXIE bit is set as `1' 1: transmitter is ready, an interrupt is asserted if 0: transmitter is not ready TXIE bit is set as `1'
5.15. Analog-to-Digital Converter (ADC)
SPMC75F2413A embeds an 8-channel ADC with 10-bit resolution. The channel inputs AN7 - AN0 of ADC shares with GPIO pins IOA7 - IOA0, respectively. When corresponding ADC channel is enabled, each pin can be controlled to disable digital function through the register, P_ADC_Channel. The output of sample hold is converted from the analog signal fed into the converter. This converter generates a result via successive approximation. The analog top reference voltage is selectable through the pin VEXTREF. The A/D Converter used for the SPMC75F2413 contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor after activation A/D conversion. The block diagram of A/D converter is shown in Figure 5-83. Figure 5-84 shows the timing diagram of ADC. The ADC has the following features: 10-bit resolution Max. 100kHz conversion rate 8 selectable input channels AN[7:0], shared pin with IOA[7:0] External reference input pin VEXTREF Four selectable ADC conversion clock: FCK/8, FCK/16, FCK/32, FCK/64 Provides conversion complete interrupt Multiple triggers to start a conversion - Software immediate start - TGRA compare match on PDC0, PDC1, TPM2 and TGRD compare match on MCP3, and MCP4 timers
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Figure 5-83 ADC equivalent circuit for SPMC75F2413A
P_ADC_Setup .ADCCS Ts1 P_ADC_Setup .ADCEN Ts2 P_ADC_Ctrl .ADCCHS
ADC clock Tsh
Sample hold
1
2
9
10
4 ADC clock > Tsh > 3 ADC clock
P_ADC_Ctrl .ADCRDY
P_ADC_Data
Ts1:The settle time of ADC chip enabled; min. 2ms. Ts2: The settle time of the changed ADC channel;Ts2 is proportional to the ADC channel input loading. min. 7us @CL=1000pF for AN7-0 ADC channel loading. Tsh: Analog input sampling period
Figure 5-84 ADC timing diagram
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The bit ADCCS is set initially to turn on the internal bias in ADC and off if Standby mode for power saving. ADCEN is the control bit to enable ADC function. The ADC clock is configured by ADCFS in P_ADC_Setup. The derived clock frequency is suggested to be less 1.5MHz for conversion precision. The ways to starting conversion have tree methods: external conversion request, auto sampling signal from Timer/PWM module (TPM) and manual ADC
conversion. These can be configured by the bits ADCEXTRG and ASPEN in P_ADC_Setup, and ADCSTR in P_ADC_Ctrl. The conversion ready status ADCRDY and interrupt flag ADCIF will set if conversion ready. Figure 5-85. The converted data can acquired through P_ADC_Data(R). The example of ADC operation is shown in
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P_ADC_Setup .ADCCS P_ADC_Setup .ADCEN P_ADC_Setup .ADCFS 0 1 2 2 3 3
Select ADC clock and the derived frequency less than 1.5MHz is suggested ADC clock P_ADC_Ctrl .ADCSTR write 1 to make a conversion. P_ADC_Ctrl .ADCCHS[2:0] 0 2 2 3 6
1 select one of channels(IOA[7:0]) as an analog signal input pin.
P_ADC_Setup .ADCEXTRG write 1 to select IOA/ADCTRG as the conversion signal IOA15/ADCTRG P_ADC_Setup .ASPEN write 1 to enable auto sampling mode Auto sampling signal P_ADC_Ctrl .ADCRDY P_ADC_Ctrl .ADCIF Write P_ADC_Ctrl.ADCIF=1 to clear this flag P_TMR0_INT .TADSE write 1 to select PDC0 as sampling clock source
Figure 5-85 AD conversion timing
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* P_ADC_Setup (0x7160)ADC Setup Register The P_ADC_Setup register control the ADC block power on or off, ADC conversion clock and event selection to trigger the start operation of ADC. User should note that the when power-on-reset occurred, the ADC block is power on (ADCCS bit is 1) and ADC function is off (ADCEN bit is 0). At meanwhile, the P_ADC_Data value is 0xFFC0 for the purpose of power saving but without ADC B15 R/W 1 ADCCS B7 R/W 0 ASPEN B15 B14 B13-B11 B10-B9 B8 B7 B6-B0 ADCCS ADCEN Reserved ADCFS ADCEXTRG ASPEN Reserved A/D converter clock selection 00: CPUCLK /8 10: CPUCLK /32 External ADC conversion request trigger from a high 1: Enable pulse on IOA15 pad Auto Sampling mode enable 0: Disable 1: Enable 01: CPUCLK /16 11: CPUCLK /64 0: Disable ADC power on ADC converter enable B14 R/W 0 ADCEN B6 R 0 B5 R 0 B13 R 0 B12 R/W 0 Reserved B4 R 0 B3 R 0 Reserved 0: un-select ADC block 0: disable ADC block 1: select ADC block 1: enable ADC block B2 R 0 B11 R/W 0 B10 R/W 0 ADCFS B1 R 0 B9 R/W 0 B8 R/W 0 ADCEXTRG B0 R 0 conversion ready signal (ADCRDY in P_ADC_Ctrl register is 0). If user sets the ADCEN to 1 at this time, the ADC block will generate the ADCRDY signal and also set the ADCIF bit in P_ADC_Ctrl register. To prevent read the incorrect ADC value; do not read the first ADC data after the ADCEN is set to 1.
Configure ADCFS to let derived frequency is less than 1.5MHz. Please refer to the bit TADSE in P_TMRx_INT (x=0~4)
* P_ADC_Ctrl(0x7161) ADC Control Register B15 R/W 0 ADCIF B7 R 0 ADCRDY B15 B14 B13-B8 B7 B6 B5-B3 B2-B0 ADCIF ADCIE Reserved ADCRDY ADCSTR Reserved ADCCHS Select ADC converter channel input 000: ADC Channel0 (IOA0) 010: ADC Channel2 (IOA2) 100: ADC Channel4 (IOA4) 110: ADC Channel6 (IOA6)
: write `1' to clear this flag
B14 R 0 ADCIE B6 R/W 0 ADCSTR
B13 R 0
B12 R 0
B11 R 0 Reserved
B10 R 0
B9 R 0
B8 R 0
B5 R 0
B4 R 0 Reserved
B3 R 0
B2 R/W 0
B1 R/W 0 ADCCHS
B0 R/W 0
ADC interrupt flag ADC interrupt enable ADC conversion ready Manual start ADC Conversion
0: interrupt Not happened 0: disable
1: interrupt happen 1: enable
0: conversion not ready, AD data 1: conversion ready, AD data is not effect 0: No Effect valid 1: START 001: ADC Channel1 (IOA1) 011: ADC Channel3 (IOA3) 101: ADC Channel5 (IOA5) 111: ADC Channel7 (IOA7)
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* P_ADC_Channel(0x7166) ADC Input Channels Select Register B15 R 0 B14 R 0 B13 R 0 B12 R 0 Reserved B7 R/W 0 ADCCH7 B15-B8 B7 B6 B5 B4 B3 B2 B1 B0 B6 R/W 0 ADCCH6 Reserved ADCCH7 ADCCH6 ADCCH5 ADCCH4 ADCCH3 ADCCH2 ADCCH1 ADCCH0 ADC Input Channel 7 Enable ADC Input Channel 6 Enable ADC Input Channel 5 Enable ADC Input Channel 4 Enable ADC Input Channel 3 Enable ADC Input Channel 2 Enable ADC Input Channel 1 Enable ADC Input Channel0 Enable 1: IOA7 as ADC channel 7 1: IOA6 as ADC channel 6 1: IOA5 as ADC channel 5 1: IOA4 as ADC channel 4 1: IOA3 as ADC channel 3 1: IOA2 as ADC channel 2 1: IOA1 as ADC channel 1 1: IOA0 as ADC channel 0 0: IOA7 as GPIO 0: IOA6 as GPIO 0: IOA5 as GPIO 0: IOA4 as GPIO 0: IOA3 as GPIO 0: IOA2 as GPIO 0: IOA1 as GPIO 0: IOA0 as GPIO B5 R/W 0 ADCCH5 B4 R/W 0 ADCCH4 B3 R/W 0 ADCCH3 B2 R/W 0 ADCCH2 B1 R/W 0 ADCCH1 B0 R/W 0 ADCCH0 B11 R 0 B10 R 0 B9 R 0 B8 R 0
* P_ADC_Data (0x7162) ADC Data Register B15 R 1 B14 R 1 B13 R 1 B12 R 1 ADCDATA B7 R 1 ADCDATA B15-B6 B5-B0 ADDATA Reserved ADC conversion data B6 R 1 B5 R 0 B4 R 0 B3 R 0 Reserved B2 R 0 B1 R 0 B0 R 0 B11 R 1 B10 R 1 B9 R 1 B8 R 1
5.16. Watchdog Timer (WDT)
The purpose of a watchdog timer is to monitor if the system operates normally. must be cleared. Within a certain period, watchdog counter If the watchdog timer is not cleared, CPU The device includes a watchdog timer (WDT) to monitor abnormal software run-away. eight-bit counter. sources. be generated. A system or CPU reset will be generated if it The watchdog timer is an Its clock can be selected from eight different is not periodically cleared by software.
assumes the program has been running in an abnormal condition and therefore, CPU will reset the system to the initial state and start running the program from beginning. It protects the system from incorrect code execution by launching a system reset when the watchdog timer overflows as a result of failure of software to clear the timer within selection time. P_System_Option.WDG. For SPMC75F2413A devices, watchdog function can be enabled or disabled by
When a counter overflow occurs, a watchdog reset will A watchdog reset can issue a system reset or To further
CPU reset according to control register settings.
ensure the settings of watchdog control register will not be modified accidentally, a special bit pattern must be written to the unused bits of watchdog control register when the settings is to be changed. Otherwise a watchdog reset will be generated if the unused bits of watchdog control register are not properly written.
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Following are the eight watchdog time-out selections. WDPS Table 5-23 WDT Time-out selections WDPS 000 001 010 WDT Clock Rate (Hz) FCK/65536 FCK/32768 FCK/16384 Time-out Time (FCK=24MHz) 699.05ms 349.52ms 174.76ms 011 100 101 110 111
WDT Clock Rate (Hz) FCK/8192 FCK/4096 FCK/2048 FCK/1024 FCK/512
Time-out Time (FCK=24MHz) 87.38ms 43.69ms 21.84ms 10.92ms 5.46ms
P_System_Option .WDG P_WatchDog_Ctrl .WDEN Clear P_WatchDog_Ctrl.WDEN if P_WatchDog_Ctrl.WDRS = 1 P_WatchDog_Ctrl .WDRS System reset CPU reset Watchdog timer
26
27
0
1
2
3
7E
7F
0
1
2
3
7E
7F
0
write P_WatchDog_Clr = $A005 to clear Watchdog Timer P_Reset_Status .WDRF
Figure 5-86 Watchdog Timing Diagram
Write P_Reset_Status = $5504 to clear this flag
* P_WatchDog_Ctrl (0x700A)Watchdog Control Register This register provides the watchdog clear timer and on/off function for firmware setting. B15 R/W 0 WDEN B7 W 0 B14 R/W 0 WDRS B6 W 0 B5 W 0 WDCHK B15 B14 B13-B8 B7-B3 WDEN WDRS Reserved WDCHK Watchdog control register check bits To change the settings of P_WatchDog_Ctrl register, "10101" must be written to these bits. Otherwise a watchdog reset will be generated. These bits will be read as `0' B2-B0 WDPS Watchdog Timer Time-out Selections Please see Table 5-23
If WDEN is set, this bit can only be cleared by system reset event, which is reset CPU and peripherals. Please refer to Table 5-7.
B13 R 0
B12 R 0
B11 R 0 Reserved
B10 R 0
B9 R 0
B8 R 0
B4 W 0
B3 W 0
B2 R/W 0
B1 R/W 0 WDPS
B0 R/W 0
Watchdog timer enable bit Watchdog reset select bit
0: Disable 0: System reset
1: Enable 1: CPU reset
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* P_WatchDog_Clr (0x700B)Watchdog Clear Register P_WatchDog_Clr register is used to clear watchdog timer, Write 0xA005 to clear watchdog timer. A watchdog reset will be generated if other value has been written. B15 R/W 0 B14 R/W 0 B13 R/W 0 B12 R/W 0 WDTCLR B7 R/W 0 B6 R/W 0 B5 R/W 0 B4 R/W 0 WDTCLR
Note: Please the bit WDRF in P_Reset_Status for reference.
B11 R/W 0
B10 R/W 0
B9 R/W 0
B8 R/W 0
B3 R/W 0
B2 R/W 0
B1 R/W 0
B0 R/W 0
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6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics DC Supply Voltage Input Voltage Range Current into Vdd Pin Current out of Vss Pin Current soured by each I/O port Current sunk by each I/O port Operating Temperature Storage Temperature
conditions see DC Characteristics.
Symbol VDD VIN IVDD IVSS IOHR IOLR TA TSTO
Min.
Typ. -
Max. 6.0(V+) V+ + 0.5 80 80 15 15 +85 +150
Unit V V mA mA mA mA
For normal operational
-0.5 -40 -50
-
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
6.2. DC Characteristics (VDD = 4.5~5.5V, TA = -40~85C)
Characteristics Operating Voltage LVR voltage Operating current Wait current Standby current Input High Level Input Low Level Output High Current Symbol Min. VDD VLVR IOP IWAIT ISTB VIH VIL IOH1 IOH2 IOL1 IOL2 RPL RPH 4.5 3.60 0.7VDD -2.0 -4.0 2.0 10 Limit Typ. 5.0 4.09 100 100 Max. 5.5 4.50 35 25 150 0.3VDD V V mA mA uA V V mA VDD = 5.0V, 6MHz X'tal, FCK=24MHz PLL on, CPU off All off, VDD = 5.0V, TA = 25 All input All input VDD = 4.5V, VOH = 4.0V (Normal drive I/O) VDD = 4.5V, VOH = 4.0V (Large drive I/O) VDD = 4.5V, VOL = 0.5V (Large drive I/O) VDD = 5.0V, VO = VDD VDD = 5.0V, VO = VSS
Unit
Test Condition
Output Low Current Input Pull-low Resistance Input Pull-high Resistance
mA K K
VDD = 4.5V, VOL = 0.5V (Normal drive I/O)
Note1: Data in "Typ" column is at 25C unless otherwise stated. Note2: Large drive I/O pins: IOA[15:8], IOB[5:0], IOB[15:12], IOC[3:0], IOC[15:10]
6.3. AC Characteristics (VDD = 4.5~5.5V, TA = -40~85C)
Characteristics Input Clock Frequency (Crystal) PLL Output Frequency Power-on Timer Period and Time of Wakeup from Standby Mode RESETB Pulse Width (low) Symbol Min. FCK FPLL TPORT TRSTB 3.0 12 Typ. 82 7.0 Unit Max. 6.0 24 200 15 MHz MHz mS uS Unit
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6.4. Analog Interface Electrical Characteristics (VDD = 5.0V, TA = -40C~85C)
Mnemonic Resolution Top Reference Voltage Top Reference Voltage Supply Current Analog Input Voltage Conversion Rate A/D Converter Analog Input Impedance (Note 2) Integral Linearity Error Differential Linearity Error Accuracy Zero Offset Error Full Scale Error Total Error Description Symbol NR_AD VRT IRT VAIN FAD RAIN(Note 2) EINL_AD EDNL_AD EZOE_AD EFSE_AD EALL_AD Min. 2 (Note 1) 0 50 Typ. 500 100 1.0 1.0 Max. 10 VDD VDD/VRT 200 30 2.0 2.0 1.5 1.5 3.0 Unit Bit V uA V KHz K LSB (Note 3) LSB LSB LSB LSB VDD=5.0V@24.0MHz Condition
Note1: The ADC performance is limited by the system's noise level, so the SPMC751F2413A can not guarantee the 10-bit accuracy when VEXTREF is 2.0V. Note2: Analog input voltage might not stabilize within the analog input sampling period (>1.5uSec) if the output impedance of the external circuit for the analog input is high enough. Therefore, it is recommended to keep the output impedance of the external circuit low. It is recommended that the impedance is less than 30K. Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.01uF to 0.1uF for the analog input pin. Figure 5-83 shows ADC equivalent circuit for reference. Note3: LSB means Least Significant Bit. With VEXTREF=5.0V, 1LSB=5.0V/2^10=4.883 mV.
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7. SPMC75F2413A EVM BOARD V1.1 SCHEMATIC
Figure 7-1 SPMC75F2413A EVM board circuit part I
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Figure 7-2 SPMC75F2413A EVM board circuit part II
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Figure 7-3 SPMC75F2413A EVM board circuit part III
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8. PACKAGE/PAD LOCATIONS
8.1. Package Information 8.1.1. 80 PIN QFP
D D1
E E1
e
b
c
L1
A2 A A1
Symbol Min. A A1 A2 b c D D1 E E1 e L1 0.010 0.098 0.012 0.004
Dimension in inch Typ. 0.107 0.014 0.006 0.913 BSC. 0.787 BSC. 0.677 BSC. 0.551 BSC. 0.031 BSC. 0.063 REF Max. 0.134 0.114 0.018 0.009
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8.1.2. 64 PIN QFP
D D1
E E1 e
b
c
L1
A2 A A1
Symbol Min. A A1 A2 b C D D1 E E1 e L1 0.010 0.098 0.014 0.004
Dimension in inch Typ. 0.107 0.015 0.006 0.913 BSC. 0.787 BSC. 0.677 BSC. 0.551 BSC. 0.039 BSC. 0.063 REF Max. 0.134 0.114 0.020 0.009
8.2. Ordering Information
Product Number SPMC75F2413A - PQ05 SPMC75F2413A - PQ04 Package Type Package form - QFP 80 Package form - QFP 64
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8.3. Storage Condition and Period for Package
Package QFP Moisture sensitivity level LEVEL 3 Max. Reflow temperature 220 +5/-0 Floor life storage condition 168Hrs @ 30/ 60% R.H. Dry pack Yes
Note1: Please refer to IPC/JEDEC standard J-STD-020A and EIA JEDEC stand JFSD22-A112 Note2: or refer to the "CAUTION Note" on dry pack bag.
8.4. Recommended SMT Temperature Profile
This "Recommended" temperature profile is a rough guideline for SMT process reference. Most of SUNPLUSIT leadframe base product choice Matte Tin and Sn/Bi for plating recipe. For PPF(Pre-Plated Frame) product with 63/37 solder paste, we recommend 240~245 for peak temperature.
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9. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Innovation Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUSIT makes no warranty, express, statutory implied or by description regarding the information in this FURTHERMORE, SUNPLUSIT MAKES NO SUNPLUSIT reserves the right to halt production or alter the publication or regarding the freedom of the described chip(s) from patent infringement. WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. specifications and prices at any time without notice. applications. information in this publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other Products described herein are intended for use in normal commercial Please note that
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by SUNPLUSIT for such applications. application circuits illustrated in this document are for reference purposes only.
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10. REVISION HISTORY
Date Feb. 15, 2006 JUL. 20, 2005 Revision # 1.1 1.0 Modify the Conversion Rate (FAD) 1. Rewrite the chapters for TPM0 ~ TPM4 module. 2. Supply detailed timing diagrams for every topic. 3. Change Operating current, Wait current and Standby current in 6.26.2 4. Add TPORT and TRSTB in 6.36.3. 5. Add analog interface electrical characteristics in 6.4. 6. Add IVDD, IVSS, IOHR, IOLR in 6.1. JUN. 17, 2004 0.1 Original Description Page 141 55~117 33~136 139 139 140 139 33
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